SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 283

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

Power Management
21.1
In this document, the generic PNX1300 name refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
PNX1300 supports power management in two ways:
• In global power-down mode, most clocks on the chip
• A block power down mechanism allows power down
21.2
Power management is software controlled and is initiat-
ed by writing to the MMIO register POWER_DOWN. Dur-
ing execution of this MMIO operation, the system is pow-
ered down without completing the MMIO operation.
When the system wakes up from power down mode, the
MMIO operation is completed.
This means that during program execution on the
DSPCPU the moment of power down is defined exactly:
any instruction before the instruction that contains the
MMIO operation is completed before entering power
down mode. The instruction containing the MMIO opera-
tion and all subsequent instructions are completed after
wake up from power down mode.
Wake-up from power down mode is effected by receiving
an interrupt (any interrupt) that passes the acceptance
criteria of the interrupt controller.
There is also wake-up from power down if a peripheral
unit asserts a memory request signal on the highway.
During power down mode the whole chip is powered
down, except the PLLs, the interrupt logic, the timers, the
wake-up logic in the MMI, and any logic in the peripheral
units and PCI bus interface that is not participating in the
power down.
Note: Writing to the global POWER_DOWN register (at
offset 0x100108) has no effect on the contents of the
BLOCK_POWER_DOWN register (at offset 0x103428),
and vice versa.
are shut down and the SDRAM main memory is
brought into low-power self-refresh mode. The power
of all on-chip peripheral blocks except for BTI (boot
and I
VIC blocks is shut off. Some peripherals can be
selectively prevented from participating in the global
power down.
of select peripheral blocks
OVERVIEW
ENTERING AND EXITING GLOBAL
POWER DOWN MODE
2
C blocks), Dcache, Icache, PCI, timers and
21.3
The on-chip peripheral units participate in global power
down. This can be a programmable option for selected
peripherals. These selected peripherals have a program-
mable MMIO control bit, the SLEEPLESS bit, that can be
used to prevent it from participating in the global power
down mode. By default every peripheral unit must partic-
ipate in power down.
The following peripheral units have the SLEEPLESS bit:
Video In, Video Out, Audio In, Audio Out, SPDO, SSI,
and JTAG.
The following peripherals do not have the SLEEPLESS
bit and always participate in power down: VLD, boot/I
and ICP.
The following peripherals do not participate in global
power down, although they must power themselves
down when they are inactive: VIC, PCI.
When a peripheral does not participate in global power
down, it can still do regular main memory traffic. Every
time a peripheral unit asserts the highway request signal,
the MMI will initiate a wake-up sequence. The CPU must
execute software that initiates a new power down of the
system. This software can be the wait-loop of the RTOS.
Programmer’s note: Since the system is awakened each
time there is a transaction on the highway, it may be in-
teresting to make a software loop that does the activation
of the POWER_DOWN mode. Then the activation is con-
ditional and most of the time done using a global vari-
able, usually set by a handler. It then becomes mandato-
ry to be sure that there are no interruptible jumps
between the time the value of the global variable is
fetched and compared by the DSPCU and the time the
conditional write to the MMIO is performed (it is the clas-
sical semaphore or test and set issue). Thus it is recom-
mended that a separate function be used with the ad-
dress of the variable as a parameter. This function needs
then to be compiled specifically without interruptible
jumps.
The wake-up from power down mode takes approxi-
mately 20 SDRAM clock cycles. This amount of time is
added to the worst case latency for memory requests
compared to the situation when the system is not in pow-
er down mode.
PRELIMINARY SPECIFICATION
EFFECT OF GLOBAL POWER DOWN
ON PERIPHERALS
by Eino Jacobs and Hani Salloum
Chapter 21
21-1
2
C