SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 405

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

PNX1300/01/02/11 Data Book
ild16x
SYNTAX
FUNCTION
DESCRIPTION
it to 32 bits, and stores the result in rdest. If the memory address computed by rsrc1 + 2×rsrc2 is not a multiple of 2,
the result of
big-endian depending on the current setting of the bytesex bit in the PCSW.
defined only for 32-bit loads and stores.
modification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written and
the data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is not
changed and
EXAMPLES
A-107
r10 = 0xd00, r30 = 1, [0xd02] = 0x22,
[0xd03] = 0x11
r50 = 0, r40 = 0xd04, r20 = 0xfffffffe,
[0xd00] = 0x84, [0xd01] = 0x33
r60 = 1, r40 = 0xd04, r20 = 0xfffffffe,
[0xd00] = 0x84, [0xd01] = 0x33
r70 = 0xd01, r30 = 1
The
The result of an access by
The
[ IF rguard ] ild16x rsrc1 rsrc2 → rdest
if rguard then {
}
if PCSW.bytesex = LITTLE_ENDIAN then
else
temp<7:0> ← mem[(rsrc1 + (2 × rsrc2) + (1 ⊕ bs)]
temp<15:8> ← mem[(rsrc1 + (2 × rsrc2) + (0 ⊕ bs)]
rdest ← sign_ext16to32(temp<15:0>)
ild16x
ild16x
bs ← 1
bs ← 0
Initial Values
ild16x
ild16x
operation loads the 16-bit memory value from the address computed by rsrc1 + 2×rsrc2, sign extends
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
is undefined but no exception will be raised. This load operation is performed as little-endian or
PRELIMINARY SPECIFICATION
has no side effects whatever.
ild16x
ild16x r10 r30 → r100
IF r50 ild16x r40 r20 → r80
IF r60 ild16x r40 r20 → r90
ild16x r70 r30 → r110
to the MMIO address aperture is undefined; access to the MMIO aperture is
Operation
Signed 16-bit load with scaled index
r100 ← 0x00002211
no change, since guard is false
r90 ← 0xffff8433
r110 undefined, since 0xd01 + 2×1 is not a
multiple of 2
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
ild16 uld16 ild16d uld16d
ild16r uld16r uld16x
Philips Semiconductors
ATTRIBUTES
SEE ALSO
Result
dmem
196
4, 5
No
—
2
3