HUFA76619D3ST Fairchild Semiconductor, HUFA76619D3ST Datasheet - Page 8

• Manufacturer Part Number: HUFA76619D3ST
• Description: MOSFET N-CH 100V 18A DPAK
• Manufacturer: Fairchild Semiconductor
• Series: UltraFET™r

Specifications of HUFA76619D3ST

• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 85 mOhm @ 18A, 10V
• Drain To Source Voltage (vdss): 100V
• Current - Continuous Drain (id) @ 25° C: 18A
• Vgs(th) (max) @ Id: 3V @ 250µA
• Gate Charge (qg) @ Vgs: 29nC @ 10V
• Input Capacitance (ciss) @ Vds: 767pF @ 25V
• Power - Max: 75W
• Mounting Type: Surface Mount
• Package / Case: DPak, TO-252 (2 leads+tab), SC-63
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SABER Electrical Model
REV 28 August 1999
template hufa76619 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 5.9e-13, cjo = 9.0e-10, tt = 1e-7,m = 0.65)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 9e-10, is = 1e-30, m = 0.9, n= 10)
m..model mmedmod = (type=_n, vto = 1.85, kp = 4, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.22, kp = 50, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.60, kp = 0.05, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.5, voff = -2.0)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.0, voff = -4.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.3, voff = 0.2)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.3)
c.ca n12 n8 = 1.3e-9
c.cb n15 n14 = 1.4e-9
c.cin n6 n8 = 7.5e-10
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1.0e-9
l.lgate n1 n9 = 1.73e-10
l.lsource n3 n7 = 6.12e-10
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = -5e7
res.rdbody n71 n5 = 1.3e-2, tc1 = 1e-5, tc2 = 0
res.rdbreak n72 n5 = 5.80e-1, tc1 = 1e-3, tc2 = -2e-5
res.rdrain n50 n16 = 3.95e-2, tc1 = 11.5e-3, tc2 = 2.6e-5
res.rgate n9 n20 = 2.95
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 1.7
res.rlsource n3 n7 = 6.1
res.rslc1 n5 n51 = 1e-6, tc1 = 3e-3, tc2 =1.0e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 23e-3, tc1 = 1e-3, tc2 =1e-6
res.rvtemp n18 n19 = 1, tc1 = -1.5e-3, tc2 = 1.0e-6
res.rvthres n22 n8 = 1, tc1 = -1.8e-3, tc2 = -6.5e-6
spe.ebreak n11 n7 n17 n18 = 117.5
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/35))** 3.7))
}
}
©2001 Fairchild Semiconductor Corporation
GATE
1
RLGATE
LGATE
9
RGATE
CA
12
20
EVTEMP
+
S1A
S1B
ESG
18
22
EGS
13
8
+
-
-
13
6
8
10
+
+
-
-
14
13
6
8
6
RSLC2
S2A
S2B
DPLCAP
EVTHRES
+
EDS
19
8
15
CB
CIN
-
+
-
5
8
5
MSTRO
14
51
21
RDRAIN
RSLC1
50
ISCL
16
8
MMED
8
RDBREAK
DBREAK
IT
RSOURCE
MWEAK
17
EBREAK
RVTHRES
RBREAK
72
11
+
HUFA76619D3, HUFA76619D3S Rev. B
-
17
18
7
+
-
18
22
RVTEMP
19
71
RLSOURCE
RLDRAIN
LSOURCE
VBAT
RDBODY
DBODY
LDRAIN
SOURCE
DRAIN
2
3