HC230F1020 Altera, HC230F1020 Datasheet
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... Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook. Altera Corporation Section I. HardCopy II Device Family Data Sheet ® II devices. These cpaters contain feature definitions of the “ ...
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... Revision History Section I–2 Preliminary HardCopy Series Handbook, Volume 1 Altera Corporation ...
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... HardCopy II devices improve on the successful and proven methodology of the two previous generations of HardCopy series devices. Altera HardCopy II devices use the same base arrays across multiple designs for a given device density and are customized using only two metal layers. ...
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... Support for high-speed external memory, including DDR and ● DDR2 SDRAM, RLDRAM II, QDRII SRAM, and SDR SDRAM Support for multiple intellectual property megafunctions from ● Altera MegaCore ® functions, and Altera Megafunction Partners SM Program (AMPP ) megafunctions Packaging Pin-compatible with Stratix II FPGA prototypes ● ...
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... The I/O pin counts include the dedicated CLK input pins, which can be used for clock signals or data inputs. (4) (5) The Quartus II I/O pin counts include an additional pin (PLLENA), which is not available as a general-purpose I/O pin. The PLLENA pin can only be used to enable the PLLs. Altera Corporation September 2008 HC210W (1) HC210 ...
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... Depending on design specific resource utilization, an opportunistic migration path may exist between this device pair. Be sure to confirm your design is a potential candidate for such a path by fitting with the Quartus II software and consulting an Altera applications engineer. 1–4 Preliminary Table 1–2. Depending on the design ...
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... Table 1–4 Revision History Table 1–4. Document Revision History (Part Date and Document Version September 2008, Updated chapter number and metadata. v2.6 June 2007, v2.5 Minor text edits. Altera Corporation September 2008 Notes 484-Pin 672-Pin 780-Pin FineLine BGA FineLine BGA (3) Flip-chip ...
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... Updated “Features” section. January 2005 Added document to the HardCopy Series Handbook. v1.0 1–6 Preliminary Changes Made Summary of Changes A minor update to the chapter, due to changes in the Quartus II software version 6.1 release. Merged Table 1-3 and Table 1-4. Altera Corporation September 2008 ...
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... Enhanced PLLs 2 Fast PLLs 2 Package (maximum 484-pin user I/O pins) (4), (5) FineLine BGA (308) Altera Corporation September 2008 2. Description, Architecture, ® ® HardCopy II devices feature an architecture that provides ® II FPGAs. HardCopy II devices make optimal use of die area and ® II design software, provide a complete, ...
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... A fine-grain architecture consisting of an array of HCells extends the die reduction and cost 2–2 Preliminary (1) HC210 HC220 EP2S30 EP2S60 EP2S60 EP2S90 EP2S90 EP2S130 HC230 HC240 EP2S90 EP2S180 EP2S130 EP2S180 Altera Corporation September 2008 ...
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... IOE IOE Fast PLL of HCells Note to Figure 2–1: (1) Figure 2–1 shows a graphical representation of the device floor plan. A detailed floor plan is available in the Quartus II software. Altera Corporation September 2008 (Figure 2–1). Note (1) M4K RAM Blocks IOE IOEs M-RAM Block Array Array Array ...
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... DSP block functions are implemented using HCells, instead of dedicated DSP blocks. M4K and M-RAM memory blocks can implement various types of memory (the same as Stratix II FPGAs), with or without parity, including true dual-port, simple dual-port, and single-port RAM, ROM, and first-in first-out (FIFO) buffers. Different Altera Corporation September 2008 ...
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... Altera Corporation September 2008 HardCopy II and Stratix II Similarities and Differences Unlike Stratix II FPGAs, the HardCopy II M4K block contents cannot be pre-loaded with a Memory Initialization File (.mif) when used as RAM. When used as ROM, HardCopy II M4K blocks are initialized to the ROM contents ...
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... Preliminary Figure 2–1. Only HCells needed to implement the customer 9 × 9 multiplier 9 × 9 two-multiplier adder (9 × 9 complex multiply) 9 × 9 four-multiplier adder 18 × 18 multiplier 18 × 18 two-multiplier adder (18 × 18 complex multiply) 18 × 18 four-multiplier adder 52-bit (18 × 18) multiplier-accumulator 36 × 36 multiplier Altera Corporation September 2008 ...
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... HardCopy II devices support all Stratix II DSP configurations (9 × × 18, and 36 × 36 multipliers) and all Stratix II DSP block features, such as dynamic sign controls, dynamic addition/subtraction, saturation, rounding, and dynamic input shift registers, except for dynamic mode switching. Altera Corporation September 2008 (Figure 2–2). In HardCopy II devices, the HCell-based logic Output ...
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... HardCopy II M4K memory blocks, the 2–8 Preliminary Up to four 18-bit independent multipliers Up to two 8-bit multiplier-accumulators One 36-bit multiplier HC210 HC220 190 190 408 0 0 875,520 3,059,712 (Table HC230 HC240 614 768 6,368,256 8,847,360 Altera Corporation September 2008 2–3). ...
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... HardCopy II and Stratix II clock control blocks support dynamic selection of the input clock from up to four possible sources, giving the designer the flexibility to choose from multiple (up to four) clock sources. Altera Corporation September 2008 Table 2–4 shows the size and features of the different RAM All Stratix II PLL features are supported by HardCopy II PLLs ...
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... M-RAM Blocks 350 MHz 589,824 64K × 8 64K × 9 32K × 16 32K × 18 16K × 32 16K × × × × 128 4K × 144 Not supported v Outputs unknown Output registers only New data available at positive clock edge Altera Corporation September 2008 ...
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... FPGA prototyping design uses the same PLL resources available in the HardCopy II device. Table 2–6. HardCopy II PLLs Available (Part Device HC210W v v HC210 Altera Corporation September 2008 (Part M4K Blocks Feature HC210W HC210 2–13), a fast PLL could be used in place of an enhanced shows which PLLs are available in each device density. ...
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... Notes to Figure 2–3: (1) The PLLs may be located in the periphery or in the core of the device. (2) This is the die-level top view of the device and is only a graphical representation of the PLL locations. 2–12 Preliminary Note (1) Fast PLLs Notes (1), ( CLK[7..4] Enhanced PLLs Altera Corporation September 2008 ...
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... I/O pins, the device uses a data channel to generate the transmitter output clock ) (txclkout . (7) If the design uses external feedback input pins, you will lose one (or two clock output pin. Altera Corporation September 2008 Table 2–7 shows the features of the different Enhanced PLL (1) m/(n × post-scale counter) ...
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... You user can either dynamically select between two PLL outputs, between two clock pins (CLKp or CLKn combination of the clock pins or PLL outputs. Clock power-down (dynamic clock enable or disable): In HardCopy II devices, you can dynamically turn the clock off user-mode. Table 2–8 lists the Availability Altera Corporation September 2008 ...
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... Single-ended LVCMOS 1.5-V LVCMOS Single-ended SSTL-2 class I Voltage referenced Altera Corporation September 2008 General purpose IOEs—The most commonly used I/O type in designs. Memory Interface IOEs—Includes features to interface with common external memory standards. High-speed IOEs—Supports high-speed data transmission and reception ...
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... General High-Speed Purpose IOEs IOEs IOEs (2) (2) (3) (3) (3) (3) (3) (3) (3) (3) v (5) (4), (6) (5) (4), (6) v Altera Corporation September 2008 ...
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... PLL_OUT output pins. LVPECL support is similar to Stratix II devices. The three types of IOEs are located in different areas of the device and are described in the following sections. HardCopy II devices have eight I/O banks, just as in Stratix II FPGAs. I/O type each bank supports. Altera Corporation September 2008 V Level (V) Memory ...
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... CLK, PLL_FB input pins & PLL_OUT output pins support differential SSTL, differential HSTL, LVDS & HyperTransport technology. CLK & PLL_FB pins support LVPECL. PLL 6 Bank 8 Bank 7 General Purpose IOEs Bank 10 (1), (2) Bank 5 General-Purpose IOEs Bank 6 General-Purpose IOEs Altera Corporation September 2008 ...
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... I/O Banks 1 & 2 Support 3.3-, PLL 1 2.5- & 1.8-V LVTTL/LVCMOS, 1.5-V PLL 2 LVCMOS, LVDS & HyperTransport Technology Bank 1 High-Speed IOEs Bank 8 PLL 8 Memory Interface IOEs Altera Corporation September 2008 Notes (1), (2) Bank 11 Bank 9 Bank 3 Memory Interface IOEs PLL 11 PLL 5 I/O banks 3 & 4 support 3.3-V, 2.5-V, 1.8-V LVTTL/ LVCMOS, 1.5-V LVCMOS, SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HSTL & ...
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... When planning I/O placement for designs targeting HardCopy II devices, care should be taken to ensure the same I/O standards are supported in the same HardCopy II I/O banks as in the Stratix II I/O banks. Bank 4 PLL 10 Bank 5 High-Speed IOEs PLL 4 PLL 3 Bank 6 High-Speed IOEs Bank 7 PLL 9 Altera Corporation September 2008 ...
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... Table 2–10. Programmable Drive Strength Support for General-Purpose IOEs (Part 3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL/LVCMOS Altera Corporation September 2008 Dedicated single-ended I/O buffers 3.3-V, 64-bit, 66 MHz PCI compliance 3.3-V, 64-bit, 133 MHz PCI-X 1.0 compliance JTAG boundary-scan test (BST) support ...
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... Output drive strength control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Open-drain outputs PCI clamping diode DQ and DQS I/O pins Double data rate (DDR) registers 3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V PCI 3.3-V PCI-X mode Altera Corporation September 2008 ...
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... Bond) HC210 484-pin FineLine BGA HC220 672-pin FineLine BGA 780-pin FineLine BGA HC230 1,020-pin FineLine BGA Altera Corporation September 2008 SSTL-2 class I and II SSTL-18 class I and II 1.8-V HSTL class I and II 1.5-V HSTL class I and II LVTTL/LVCMOS SSTL-2 class I and II SSTL-18 class I and II 1 ...
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... I/O Standard Programmable Drive Strength Options (mA) If on-chip series termination is enabled, programmable drive strength support is not available. Number of Number of ×16/×18 Groups ×32/×36 Groups Table 2–12 12, 16, 20 12, 16 16 16, 18 10, 12 16, 18 10, 12 16, 18, 20 Altera Corporation September 2008 ...
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... The following I/O standards are supported when using high-speed IOEs: ■ ■ ■ ■ ■ ■ Altera Corporation September 2008 Dedicated single-ended I/O buffers Differential I/O buffer JTAG BST support On-chip driver series termination (non-calibrated) On-chip termination for differential I/O standards ...
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... Preliminary HC220 HC230 672-Pin 780-Pin 1,020-Pin FineLine FineLine FineLine BGA BGA BGA I/O Standard Programmable Drive Strength Options (mA) Table 2–13 provides the Notes (1), (2) HC240 1,020-Pin 1,508-Pin FineLine FineLine BGA BGA 88 116 92 116 Table 2–14 Altera Corporation September 2008 ...
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... For more information about which power-up modes HardCopy II devices support, refer to the Power-Up Modes and Configuration Emulation in HardCopy Series Devices chapter in the HardCopy Series Handbook. Altera Corporation September 2008 HardCopy II devices do not support FPGA configuration emulation and other configuration modes, including remote system upgrades and design security using configuration bitstream encryption ...
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... Updated Figures 2–4, 2–5, and 2–6. January 2005, Added document to the HardCopy Series Handbook. v1.0 2–28 Preliminary shows the revision history for this chapter. Changes Made Table 2–4. Summary of Changes — — — — — — — Altera Corporation September 2008 ...
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... The TDO output is powered by V HardCopy II devices support the JTAG instructions shown in Table 3–1. HardCopy II JTAG Instructions (Part JTAG Instruction SAMPLE/PRELOAD EXTEST BYPASS Altera Corporation September 2008 3. Boundary-Scan Support ® II structured ASICs provide Joint Test Action Group Instruction Code 00 0000 0101 ...
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... The BSDL files for HardCopy II devices are different from the corresponding Stratix BSDL files for IEEE Std. 1149.1- compliant Hardcopy II devices, visit the Altera website at www.altera.com. The HardCopy II device instruction register length is 10 bits and the USERCODE register length is 32 bits. The USERCODE registers are not reprogrammable and are mask-programmed ...
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... IDCODE is always 1. The generic HardCopy II BSDL file you can download from the Altera website at www.altera.com. The PIN file for your design from the Quartus II software. Boundary-Scan Register Length 1050 1050 1530 ...
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... For more information on the BSDLCustomizer tool, refer to the BSDLCustomizer User Guide that you can download with the BSDLCustomizer tool from the Altera website at www.altera.com. Figure 3–1 Figure 3–1. HardCopy II JTAG Waveforms ...
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... For more information on JTAG or boundary-scan testing, refer to AN 39: IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices. 1 Document Table 3–5 Revision History Table 3–5. Document Revision History (Part Date and Document Version September 2008, Updated chapter number and metadata. v2.4 June 2007, v2.3 ● ...
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... HardCopy Series Handbook, Volume 1 Table 3–5. Document Revision History (Part Date and Document Version May 2005, v2.0 Updated Table 3-2. January 2005 Added document to the HardCopy Series Handbook. v1.0 3–6 Preliminary Changes Made Summary of Changes — — Altera Corporation September 2008 ...
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... J Notes to Table 4–1: (1) Refer to the Operating Requirements for Altera Devices Data Sheet for more information. (2) Conditions beyond those listed in operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. (3) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply. ...
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... Maximum Duty Cycles 100% 90% 50% 30% 17% 10% (Part Minimum Maximum Unit 1.15 1.25 V (6) 3.135 3.465 V (3.0) (3.6) 2.375 2.625 V 1.71 1.89 V 1.425 1.575 V 3.135 3.465 V 1.15 1.25 V 1.15 1.25 V -0.5 4 CCIO Altera Corporation September 2008 ...
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... I V supply current CCINT0 CCINT (standby supply current CCPD0 CCPD (standby) Altera Corporation September 2008 Conditions For commercial use For industrial use must rise monotonically. CC CCPD shows the HardCopy II device family’s DC electrical Note (1) Conditions Device Minimum Typical Maximum ...
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... OH (Part Unit (3) (5) — (3) (5) — — 3 (3) (5) mA (3) (5) — (3) (5) — kΩ kΩ 100 kΩ 150 kΩ 170 kΩ — kΩ . CCIO Minimum Maximum Unit 3.135 3.465 V 1.7 4.0 V -0.3 0.8 V 2.4 — V Altera Corporation September 2008 ...
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... HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information. Table 4–7. 2.5-V I/O Specifications (Part Symbol Parameter (1) V Output-supply voltage CCIO V High-level input voltage IH V Low-level input voltage IL V High-level output voltage OH Altera Corporation September 2008 Conditions Minimum = 4 mA (2), ( Table 2–10, Table 2–12, and Conditions — — — ...
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... V — -0 (2), (3) I 0.75 × Maximum Unit — 0.4 V Maximum Unit 1.71 1.89 V 2.25 V CCIO -0.3 0.35 × CCIO – 0.45 — V — 0.45 V Maximum Unit 1.575 0.3 V CCIO CCIO 0.35 × CCIO — V CCIO Altera Corporation September 2008 ...
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... HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information. Figure 4–1 waveforms, respectively, for all differential I/O LVPECL and HyperTransport technology. Figure 4–1. Receiver Input Waveforms for Differential I/O Standards Single-Ended Waveform Differential Waveform (Mathematical Function of Positive & Negative Channel) Altera Corporation September 2008 Conditions Minimum = 2 mA (2), (3) I — ...
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... Minimum Typical — 2.375 — — 100 — 200 = 100 Ω R 250 L = 100 Ω R 1.125 L — 90 Positive Channel ( Negative Channel ( Ground p − Maximum Unit 2.5 2.625 V 350 900 mV 1,250 1,800 mV — 450 mV — 1.375 V Ω 100 110 Altera Corporation September 2008 ...
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... V (peak- Input differential voltage ID swing to-peak) (single-ended) V Input common mode ICM voltage V Output differential voltage OD (single-ended) V Output common mode OCM voltage Altera Corporation September 2008 Note (1) Conditions Minimum — 3.135 (2) — 100 — 200 = 100 Ω R 250 L = 100 Ω R 0.84 L — ...
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... Maximum 100 110 , not V CCINT Typical Maximum 2.5 2.625 3.3 3.465 300 600 900 385 600 845 400 600 820 — — 75 440 600 780 — — 100 110 , not V CCINT Altera Corporation September 2008 Unit Ω . CCIO Unit Ω . CCIO ...
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... Termination voltage TT V High-level DC input voltage IH(DC) V Low-level DC input voltage IL(DC) V High-level AC input voltage IH(AC) V Low-level AC input voltage IL(AC) V High-level output voltage OH Altera Corporation September 2008 Conditions Minimum — 3 — 0.5 × V CCIO — -0 -500 µA 0.9 × V OUT CCIO I = 1,500 µA — ...
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... V – 0.475 V TT Typical Maximum Unit 1.8 1.89 V 0.9 0.945 0.04 V REF REF — — V — V – 0.125 V REF — — V — V – 0.25 V REF — — V — 0.28 V Typical Maximum Unit 1.8 1.89 V — — V Altera Corporation September 2008 ...
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... I/O Structure and Features section of the Description, Architecture, and Features chapter in volume 1 of the HardCopy Series Devices Handbook. (2) Drive strength varies based on pin location. Refer to the Description, Architecture, and Features chapter in the HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information. Altera Corporation September 2008 Conditions Minimum — ...
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... REF — — — V – 0.35 REF — — — V – 0.76 TT Typical Maximum 2.5 2.625 — — ) – 0.2 — 0.2 CCIO/2 — — 0.5 × — V CCIO ±200 — ) – 0.2 — 0.2 CCIO/2 Altera Corporation September 2008 Unit ...
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... REF V Termination voltage high-level input voltage IH (DC low-level input voltage IL (DC high-level input voltage IH (AC low-level input voltage IL (AC) V High-level output voltage OH Altera Corporation September 2008 Conditions Minimum — 1.425 — 0.713 — 0.713 — 0.1 REF — -0.3 — 0.2 REF — ...
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... V Typical Maximum Unit 1.5 1.575 V — — V — 0.9 V — — V — 0.9 V Typical Maximum Unit 1.8 1.89 V 0.9 0.95 V 0.9 0.95 V — — V — V – 0.1 V REF — — V — V – 0.2 V REF — — V Altera Corporation September 2008 ...
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... HardCopy II Device Family Data Sheet section in volume 1 of the HardCopy Series Handbook for more information. Table 4–27. 1.8-V Differential HSTL Specifications (Part Symbol Parameter V I/O supply voltage CCIO V DC input differential voltage DIF (DC common mode input voltage CM (DC) Altera Corporation September 2008 Conditions Minimum = -8 mA (1), (2) I — OL Conditions Minimum — 1.71 — ...
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... Typical Maximum Unit — 0.6 V CCIO — 0.9 2.5 V 3.3 V Min Max Min Max 50 — 70 — -50 — -70 — — 300 — 500 — -300 — -500 1.70 0.80 2.00 Altera Corporation September 2008 V V Unit µA µA µA µA V ...
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... The resistance tolerances for calibrated SOCT and POCT are at the time of initial of calibration. If the temperature or voltage changes over time, the tolerance may also change. (3) This table applies only to the HC210W device. Altera Corporation September 2008 On-Chip Termination Specifications defines the specification for internal termination specification ...
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... Commercial Max V = 3.3/2.5 V ± 3.3/2.5 V ± 3.3/2.5 V ± 3.3/2.5 V ± 1.8 V ± 1.8 V ± 1.8 V ± 1.8 V ± 1.5 V ± 1.5 V ± Resistance Tolerance Industrial Unit Max ± ± ± ± ± ± ± ± ± ± Altera Corporation September 2008 ...
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... Input capacitance on I/O pins in I/O MIIO banks supporting memory interface IOEs. C Input capacitance on I/O pins in I/O HSIO banks supporting high-speed IOEs. C Input capacitance on top/bottom clock CLKTB input pins CLK[4..7] and CLK[12..15]. Altera Corporation September 2008 Notes (1), (3), (4) Conditions Commercial Max V = 3.3/2.5 V ± 30 CCIO ...
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... MHz 500 500 MHz 500 500 MHz 500 500 MHz — 500 MHz — 500 MHz — 500 MHz — 500 MHz — 500 MHz — 500 MHz — 500 MHz — 500 MHz — 500 MHz Altera Corporation September 2008 ...
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... This I/O standard is only supported on the DQS, CLK, and PLL_FB input pins. (2) For HC210 and HC220, differential HSTL/SSTL input is supported on top/bottom PLL_FB, the top clock pins and (3) DQS pins located on the top I/Os. Altera Corporation September 2008 High General CLK CLK ...
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... Altera Corporation September 2008 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ...
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... Drive I/O Standard Interface Strength IOEs 3.3-V LVTTL (3) 3.3-V LVCMOS (3) 1040 Altera Corporation September 2008 Memory High General Interface Speed Purpose [0..3, IOEs IOEs IOEs 8..11] — 320 — and 4–36 show the maximum output toggle rates of General Purpose High IOEs ...
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... MHz — 150 150 MHz — 250 250 MHz — 300 300 MHz — 400 400 MHz — 550 550 MHz — 200 200 MHz — 350 350 MHz — 400 400 MHz — 500 500 MHz Altera Corporation September 2008 ...
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... LVDS — HyperTransport — LVPECL — Differential 8 mA SSTL2 class (3) (5) Differential 16 mA SSTL2 class (3) (5) ( Altera Corporation September 2008 General Purpose High IOEs Speed Bottom Right IOEs Column Row 300 — — — 450 — — — 600 — ...
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... MHz — 700 700 MHz — 500 500 MHz — 500 500 MHz — 550 550 MHz — 300 300 MHz — 500 500 MHz — 650 650 MHz — 700 700 MHz — 700 700 MHz Altera Corporation September 2008 ...
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... Table 4–36. HardCopy II Maximum Output Clock Rate for HC210W Devices Memory Drive I/O Standard Interface Strength 3.3-V LVTTL (3) 3.3-V LVCMOS (3) Altera Corporation September 2008 General Purpose High IOEs Speed Bottom Right IOEs Column Row 600 — — — 600 — — — 650 — — ...
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... MHz — 105 105 MHz — 175 175 MHz — 210 210 MHz — 220 220 MHz — 230 230 MHz — 140 140 MHz — 220 220 MHz — 220 220 MHz — 350 350 MHz Altera Corporation September 2008 ...
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... Differential SSTL2 8 mA (5) class I ( Differential SSTL2 16 mA class Differential 4 mA SSTL18 class I ( (3) Altera Corporation September 2008 General Purpose High IOEs Speed Bottom Right IOEs IOEs Column Row 210 — — — 210 — — — 220 — — — ...
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... MHz — 150 150 MHz — 160 160 MHz — 170 170 MHz — 180 180 MHz — 190 190 MHz — 170 170 MHz — 170 170 MHz — 170 170 MHz CLK PLL_OUT , and memory Altera Corporation September 2008 ...
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... OCT 25 Ω Differential SSTL-18 Class II (3) OCT 50 Ω 1.8-V Differential (3) HSTL Class I OCT 25 Ω 1.8-V Differential HSTL Class II (3) Altera Corporation September 2008 and 4–38 show the maximum output toggle rates of General Purpose High IOEs Speed Bottom Right IOEs Column Row ...
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... MHz 245 245 245 MHz 190 190 190 MHz — 280 280 MHz — 280 280 MHz — 230 230 MHz — 220 220 MHz — 190 190 MHz — 270 270 MHz — 210 210 MHz Altera Corporation September 2008 ...
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... These numbers are preliminary and pending further silicon characterization. HighSpeed I/O Table 4–39 Specifications Table 4–39. HighSpeed Timing Specifications and Definitions (Part HighSpeed Timing Specifications HSCLK J Altera Corporation September 2008 General Purpose High IOEs Speed Bottom Right IOEs Column Row 280 — ...
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... Min Typ Max Unit 16 — 320 MHz 16 — 320 MHz 150 — 320 MHz 150 — 640 Mbps (4) — 640 Mbps (4) — 320 Mbps 150 — 640 Mbps — — 240 ps 400 — — ps (5) — — ps Altera Corporation September 2008 ...
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... The I/O differential buffer and input register do not have a minimum toggle rate. (5) Contact the Altera Applications Group for more information. Table 4–41 HC220, HC230 and HC240 HardCopy II devices. Table 4–41. HardCopy II High-Speed I/O Specifications for HC210, HC220, HC230 and HC240 Devices ...
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... Number of repetitions — — — — 256 — — 256 — — 256 — — 256 — — — 256 — — Altera Corporation September 2008 ...
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... Duty cycle for external clock output OUTDUTY (when set to 50%). f Scanclk frequency SCANCLK t Time required to reconfigure scan CONFIGEPLL chains for enhanced PLLs f PLL external clock output OUT_EXT frequency Altera Corporation September 2008 and 4–43 describe the HardCopy II PLL specifications when Min Typ 2 — 2 — 2 — 40 — ...
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... Unit ms ms MHz MHz MHz MHz MHz % Altera Corporation September 2008 ...
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... PLL closed loop bandwidth CLBW t Time required for the PLL to lock from the LOCK time it is enabled or the end of the device configuration t Accuracy of PLL phase shift PLL_PSERR t Minimum pulse width on areset signal. ARESET Altera Corporation September 2008 Description Min — — 300 300 150 150 4 ...
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... HC210 / HC220 / HC230 / HC240 Ind (I) Com (C) 133 200 133 267 133 250 (4) 133 250 specification for Static-PHY and Auto-PHY since the MAX Typ Max 500 — — Note (1) (3) Ind (I) 200 233 (5) 233 (4) 233 Altera Corporation September 2008 Unit ns Unit MHz MHz MHz MHz ...
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... Table 4–46. DQS Delay Buffer Maximum Delay in Fast Timing Model DLL Frequency Mode Maximum Delay Per Delay Buffer Table 4–47. DQS Period Jitter Specifications for DLL-Delayed Clock (tDQS_JITTER) Notes to (1) (2) Altera Corporation September 2008 External Memory Interface Specifications through 4–51 contain HardCopy II device specifications for Frequency Range ...
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... HC240 device is 105 ps or ± 52.5 ps. Delay stages used for requested DQS phase shift are reported in your project’s Compilation Report in the Quartus II software. DQS Phase Jitter Unit 120 ps Unit 120 ps Altera Corporation September 2008 ...
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... The hot socketing feature in HardCopy II devices allow: ■ ■ ■ ■ Altera Corporation September 2008 Note (1) Mode ×4 DQ per DQS ×9 DQ per DQS ×18 DQ per DQS × ...
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... Electrostatic Electrostatic discharge (ESD) protection is a design practice that is integrated in Altera FPGAs and structured ASIC devices. HardCopy II Discharge devices are no exception, and they are designed with ESD protection on all I/O and power pins. 4–46 and V ). For mixed-voltage environments, you can drive ...
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... I/O pin due to an ESD charge event. This can cause the N+ (Drain)/PSubstrate junction of the N-channel drain to break down and the N+ (Drain)/P-Substrate/N+ (Source) intrinsic bipolar transistor turns on to discharge ESD current from I/O pin to GND. Altera Corporation September 2008 shows a typical HardCopy II CMOS I/O buffer structure Electrostatic Discharge ...
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... V (0 the voltage drop across a diode), the intrinsic P-Substrate/N+ drain diode is forward biased. Hence, the discharge ESD current path is from GND to the I/O pin, as shown in Figure 4–5. ESD Protection During Negative Voltage Zap 4–48 Figure 4–4) shows the ESD current discharge path Figure 4–5. Altera Corporation September 2008 ...
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... Details of ESD protection are also outlined in the Hot-Socketing and Power-Sequencing Feature and Testing for Altera Devices white paper located on the Altera website at www.altera.com. f For information on ESD results of Altera products, please see the Reliability Report on the Altera website at www.altera.com. Document Table 4–52 Revision History Table 4– ...
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... HardCopy Series Handbook, Volume 1 4–50 Altera Corporation September 2008 ...
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... HardCopy II Design Benefits Designing with HardCopy II structured ASICs offers substantial benefits over other structured ASIC offerings: ■ ■ ■ ■ Altera Corporation September 2008 5. Quartus II Support for HardCopy II Devices ® ® HardCopy II devices feature 1.2- process technology, “HardCopy II Development Flow” on page 5–3 “ ...
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... HardCopy II companion revisions, change revisions to use, and compare revisions for equivalency. HardCopy II Advisor—The HardCopy II Advisor helps you follow the necessary steps to successfully submit a HardCopy II design to Altera’s HardCopy Design Center. 1 The HardCopy II Advisor is similar to the Resource Optimization Advisor and Timing Optimization Advisor. ...
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... Both of these flows are illustrated at a high level in features in the HardCopy II Utilities menu assist you in completing your HardCopy II design for submission to Altera’s HardCopy Design Center for back-end implementation. Altera Corporation September 2008 HardCopy II Device Preliminary Timing—The Quartus II software performs a timing analysis of HardCopy II devices based on preliminary timing models and Fitter placements ...
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... Create and compile the HardCopy II companion revision Compare the HardCopy II companion revision compilation to the Stratix II device compilation provides an overview highlighting the development process Design Stratix II Second Select HardCopy II No Device & Stratix II Companion Device Complete HardCopy II (2) Device First Flow Altera Corporation September 2008 ...
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... When you are satisfied with the compilation results and the choice of Stratix II and HardCopy II devices, on the Assignments menu, click Settings. In the Category list, select Device. In the Device page, select a HardCopy II companion device. Altera Corporation September 2008 Prepare Stratix II Design Select Stratix II Companion Device ...
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... For more information about the overall design flow using the Quartus II software, refer to the Introduction to Quartus II manual on the Altera website at www.altera.com. Designing the HardCopy II Device First The HardCopy II family presents a new option in designing unavailable in previous HardCopy families. You can design your HardCopy II device first and create your Stratix II FPGA prototype second in the Quartus II software ...
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... Stratix II devices. This guide is found in the Fitter folder of the Compilation Report. example of the HardCopy II Device Resource Guide. Refer to for an explanation of the color codes in Altera Corporation September 2008 HardCopy II Device Resource Guide Prepare HardCopy II Design Select Stratix II Companion Device ...
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... Stratix II design. The HardCopy II device package must be compatible with the Stratix II device package. A logic resource usage greater than 100 ratio greater than 1/1 in any category indicates that the design does not fit in that particular HardCopy II device. 5–8 Altera Corporation September 2008 ...
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... For more information about the HardCopy II device resources, refer to the Introduction to HardCopy II Devices and the Description, Architecture and Features chapters in the HardCopy II Device Family Data Sheet in the HardCopy Series Handbook. Altera Corporation September 2008 HardCopy II Device Resource Guide (1) Device Resources The resource quantity is within the range of the HardCopy II device and the design can likely migrate if all other resources also fit ...
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... Stratix II EP2S130F1020 device. Based on the report, the HC230F1020 device in the 1,020-pin FineLine BGA is an appropriate HardCopy II device to migrate to. If the HC230F1020 device is not specified as a migration target during the compilation, its package and migration compatibility is rated orange, or Medium. The ...
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... You can also specify your HardCopy II companion device using the following tool command language (Tcl) command: set_global_assignment -name\ DEVICE_TECHNOLOGY_MIGRATION_LIST <HardCopy II Device Part Number> For example, to select the HC230F1020 device as your HardCopy II companion device for the EP2S130F1020C4 Stratix II FPGA, the Tcl command is: set_global_assignment -name\ ...
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... Enable Design Assistant to Run During Compile You must use the Quartus II Design Assistant to check all HardCopy series designs for design rule violations before submitting the designs to the Altera HardCopy Design Center. Additionally, you must fix all critical and high-level errors. 1 5–12 ...
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... Analyzer is no longer supported and the HardCopy Design Center will not accept any designs which use Classic Timing Analyzer for timing closure. If you are still using the Classic Timing Analyzer, Altera strongly recommends that you switch to TimeQuest. Altera Corporation September 2008 HardCopy II Recommended Settings in the Quartus II Software 5– ...
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... The TimeQuest Timing Analyzer is a complete static timing analysis tool that you can use as a sign-off tool for Altera FPGAs and structured ASICs. Setting Up the TimeQuest Timing Analyzer If you want use TimeQuest for timing analysis, from the Assignments tab ...
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... For more information about TimeQuest, refer to the Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook on the Altera website at www.altera.com. Constraints for Clock Effect Characteristics The create_clock, create_generated_clock commands create ideal clocks and do not account for board effects. In order to account for clock effect characteristics, you can use the following commands: ■ ...
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... In this case, you can use either the -overwrite command to overwrite the previous clock uncertainty command or manually remove them by using the remove_clock_uncertainty command. Table Description Short help Long help with examples and possible return values Creates PLLJ_PLLSPE_INFO.txt file Overwrites previously performed clock uncertainty assignments 5–2: Altera Corporation September 2008 ...
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... Altera strongly recommends that you use the derive_clock_uncertainty command in the HardCopy II revision. The HardCopy Design Center will not be accepting designs that do not have clock uncertainty constraint by either using the derive_clock_uncertainty command or the HardCopy II Clock Uncertainty Calculator, and then using the set_clock_uncertainty command ...
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... For more information about using the PowerPlay Power Analyzer, refer to the Quartus II PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook on the Altera website at Incremental Compilation The use of the Quartus II Incremental Compilation in the Stratix II FPGA is supported when migrating a design to a HardCopy II device. ...
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... Manager and difficult to manage since ECOs are often implemented as last minute changes to your design. Chip Planner Altera Corporation September 2008 Performing ECOs with Change Manager and Chip Planner The first compilation after migration to a companion device requires a full compilation (all partitions are compiled), but subsequent compilations can be incremental if changes to the source RTL are not required ...
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... HardCopy Series Handbook, Volume 1 With the Altera significantly. When changes are made to your design as ECOs, you do not have to perform a full compilation in the Quartus II software. Instead, you would make changes directly to the post place-and-route netlist, generate a new programming file, test the revised design by performing a gate-level simulation and timing analysis, and proceed to verify the fix on the system (if you are using a Stratix II FPGA as a prototype) ...
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... Settings Between Stratix II and HardCopy II Devices. Table 5–3 Table 5–3. Implementation Suggestions for Various Changes (Part LUTMASK changes Make/Delete LC_COMB Altera Corporation September 2008 Performing ECOs with Change Manager and Chip Planner I/O creation, deletion, and moves I/O property changes (for example, I/O standards, delay chain settings, etc ...
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... Compile the design on the initial device. Migrate the design from the initial device to the target device in the companion revision. Compile the companion revision. Perform a Revision Compare operation. The two revisions should pass the Revision Compare. Suggested Implementation Altera Corporation September 2008 ...
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... Altera Corporation September 2008 Make changes in one revision using the Chip Planner tools (Chip Planner, Resource Property Editor, and Change Manager), then verify and export these changes. The procedure for doing this is as follows: a. Make changes using the Chip Planner tool. ...
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... For more information about using Chip Planner, refer to the Quartus II Engineering Change Management with Chip Planner chapter in volume 3 of the Quartus II Handbook at www.altera.com. Formal Third-party formal verification software is available for your HardCopy II design. Cadence Encounter Conformal verification software Verification of is used for Stratix II and HardCopy II families, as well as several other Altera product families ...
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... Figure 5–9. HardCopy II Utilities Menu Altera Corporation September 2008 5–9. To access this menu, on the Project menu, click HardCopy II Create or update HardCopy II companion revisions Set which HardCopy II companion revision is the current revision Generate a HardCopy II Handoff Report for design reviews ...
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... Compare HardCopy II Companion Revisions must have been executed ● Compilation of both revisions must be completed ● Compare HardCopy II Companion Revisions must have been executed ● Generate HardCopy Handoff Report must have been executed None Altera Corporation September 2008 ...
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... On the Project menu, point to HardCopy II Utilities and click Set Current HardCopy II Companion Revision Altera Corporation September 2008 Although you can create multiple project revisions, Altera recommends that you maintain only one Stratix II FPGA revision once you have created the HardCopy II companion revision. ...
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... The Quartus II software contains preliminary timing models for HardCopy II devices and you can gauge how much performance improvement you can achieve in the HardCopy II device compared to the Stratix II FPGA. Altera verifies that the HardCopy II Companion Device timing requirements are met in the HardCopy Design Center. ...
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... Comparing HardCopy II and Stratix II Companion Revisions Altera uses the companion revisions in a single Quartus II project to maintain the seamless migration of your design from a Stratix II FPGA to a HardCopy II structured ASIC. This methodology allows you to design with one set of Register Transfer Level (RTL) code to be used in both Stratix II FPGA and HardCopy II structured ASIC, guaranteeing functional equivalency ...
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... Generate a Handoff Report. 11. Archive Handoff Files and send to Altera. 5–30 Compile both the Stratix II and HardCopy II revisions of your design Run the Compare HardCopy II Revisions utility Generate the HardCopy II Handoff Report Select a Stratix II device. Select a HardCopy II device. Turn on the Design Assistant. Set up timing constraints. ...
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... HardCopy II development through Stratix II FPGA prototyping, then completes the comparison archiving and handoff to Altera. When your design uses the Stratix II FPGA as your starting point, Altera recommends following the Advisor guidelines for your Stratix II FPGA until you complete the prototype revision. ...
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... Figure 5–13 selected. Figure 5–13. HardCopy II Advisor with Stratix II Selected Figure 5–14 selected. Figure 5–14. HardCopy II Advisor with HardCopy II Device Selected 5–32 shows the HardCopy II Advisor with the Stratix II device shows the HardCopy II Advisor with the HardCopy II device Altera Corporation September 2008 ...
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... You can see the placement of a DSP block constructed of HCell Macros, various logic HCell Macros, and an M4K memory block. A labeled close-up view of this region is shown in Altera Corporation September 2008 shows an example of the HC230F1020 device floorplan. Figure HardCopy II Utilities Menu 5–16. 5–33 ...
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... Quartus II software provide you with the tools necessary to complete your Stratix II FPGA prototype and HardCopy II structured ASIC design. The addition of the HardCopy II companion revisions feature to the process allows for rapid development and verification that your HardCopy II design is functionally equivalent to your Stratix II FPGA prototype. 5–34 Altera Corporation September 2008 ...
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... May 2005 Added information on support for HardCopy II devices in v2.0 version 5.0 of the Quartus II software. January 2005 Added document to the HardCopy Series Handbook. v1.0 Altera Corporation September 2008 shows the revision history for this chapter. Changes Made Document Revision History Summary of Changes — ...
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... HardCopy Series Handbook, Volume 1 5–36 Altera Corporation September 2008 ...
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... Command-Line Scripting chapter in volume 2 of the Quartus II Handbook. f For more information on the Quartus II Tcl implementation, refer to the Tcl Reference Manual and the Tcl Scripting chapter of the Quartus II Handbook. Altera Corporation September 2008 6. Script-Based Design for HardCopy II Devices II software includes a set of command-line executables, ® ...
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... Line Executables section of the Quartus II Scripting Reference Manual. quartus_sim The Quartus II Simulator. For more information, refer to Command-Line Executables section of the Quartus II Scripting Reference Manual. 6–2 Description quartus_sh quartus_sta quartus_tan quartus_cdb in the Command- quartus_sim Altera Corporation September 2008 Table 6–1. in the in the ...
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... Tcl statement is executed: tcl> load_package flow 1 Table 6–2. Tcl Package Support in Quartus II Executables Executable Name Supported Tcl Package quartus_sta Altera Corporation September 2008 Tcl Support in the Quartus II Software Table 6– important to note that not all executables support all Tcl packages. (Part ...
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... Not Loaded Not Loaded Not Loaded Not Loaded Loaded Loaded Not Loaded Loaded Not Loaded Not Loaded Not Loaded Loaded Not Loaded Not Loaded Loaded Loaded Not Loaded Loaded Not Loaded Loaded Loaded Loaded Loaded Table 6–2 is Altera Corporation September 2008 ...
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... HardCopy II design flow. !#/bin/csh quartus_sh --flow compile %1 quartus_cdb %1 --create_companion=%1_hcii quartus_sh --flow compile %1 -c %1_hcii quartus_cdb --compare=%1_hcii % Altera Corporation September 2008 Tcl Support in the Quartus II Software Description ® II Analyzer. 6–5 ...
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... Verifying the Stratix II FPGA prototype Migrating the prototype design to a HardCopy II design Compiling the HardCopy II design Transferring your HardCopy II files to the Altera 6–1. To begin a design, create a new project and revision for the Create a HardCopy II companion revision for the FPGA prototype. All design settings and constraints are automatically migrated to the new companion revision ...
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... If there are no mismatches, you can prepare the HardCopy II design files for transfer to the Altera Design Center. In addition to design verification in the Quartus II software, the flow can generate files required to perform Static Timing Analysis (STA) in Synopsys’ ...
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... The device family and part code can be set later using the set_global_assignment command. For example, to create 6–8 Figure 6–1 begins with a Stratix II FPGA prototype 6–1. [-part <part>] [-revision <revision_name>] \ <project_name> Figure 6–1 Altera Corporation September 2008 ...
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... Quartus II project using the project_close command. This ensures that any changes you have made to your project are written to the Quartus II QSF file. The syntax for the project_close command is: tcl> project_close [-dont_export_assignments] Altera Corporation September 2008 demo_design.db_info [-revision <revision_name>] <project_name> good practice to have consistent names for the Stratix II and HardCopy II revisions of your project ...
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... Close project demo_design and write any changes to settings to ## demo_design.qsf project_close ## End of script f For more information on these and other useful project-related commands, refer to the Project section in the Tcl Packages and Commands chapter in the Quartus II Scripting Reference Manual. 6–10 If the Project does not Already Altera Corporation September 2008 ...
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... Stratix II and HardCopy II phases of the design. For first-time users, this can provide a powerful guide for successfully completing your HardCopy II project. Altera Corporation September 2008 Specify design source files (Verilog, VHDL, AHDL, EDIF, and BDF files) ...
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... ENABLE_RECOVERY_REMOVAL_ANALYSIS ENABLE_CLOCK_LATENCY 6–12 Value Description <value> Verilog file name. VHDL file name. Altera HDL file name. EDIF file name. Altera schematic file name. Device family name, for example, Stratix II. Prototype FPGA target device name. Top-level design entity or module name. HardCopy II target device name. ...
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... C4. The two-character speed grade is appended to the Stratix II part name to form the value string for the DEVICE variable. Table 6–5. Stratix II Prototype Options for HardCopy II Altera Corporation September 2008 Table Table 6–5 ...
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... Table 6–5. Stratix II Prototype Options for HardCopy II The following two Tcl commands demonstrate setting the DEVICE and DEVICE_TECHNOLOGY_MIGRATION_LIST variables. tcl> set_global_assignment -name DEVICE EP2S90F1020C4 tcl> set_global_assignment -name \ 6–14 HardCopy II Part HC230F1020C HC2401020C HC240F1508C DEVICE_TECHNOLOGY_MIGRATION_LIST HC230F1020C (Part Stratix II Prototype Part EP2S90F1020C3 EP2S90F1020C4 EP2S90F1020C5 EP2S90F1020I4 EP2S130F1020C3 EP2S130F1020C4 EP2S130F1020C5 ...
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... For more information on the Design Assistant, refer to the Design Guidelines for HardCopy II Devices chapter in volume 1 of the HardCopy Series Handbook and the Quartus Support for HardCopy II Devices chapter in the Quartus II Handbook. Altera Corporation September 2008 -name ENABLE_DRC_SETTINGS ON Making Global Assignments 6–15 ...
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... FAMILY "Stratix II" set_global_assignment -name DEVICE EP2S90F1020C4 set_global_assignment -name TOP_LEVEL_ENTITY demo_design ## HardCopy II Companion Revision and Target Settings ## ================================================== set_global_assignment -name COMPANION_REVISION_NAME \ set_global_assignment -name DEVICE_TECHNOLOGY_MIGRATION_LIST HC230F1020 ## Design Assistant Assignments and Settings Required for HardCopy II ##============================================================== set_global_assignment -name ENABLE_DRC_SETTINGS ON set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name REPORT_IO_PATHS_SEPARATELY ON ## The following assignments are Classic Timing Analyzer only ## and are not used by TimeQuest ...
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... Making I/O Because of the complex rules governing the use of programmable I/O cells and their availability for specific pins and packages, Altera highly Assignments recommends that I/O assignments are completed using the Pin Planning tool and the Assignment Editor in the Quartus II GUI. These tools ensure that all of the rules regarding each pin and I/O cell are applied correctly ...
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... Memory clock interface Memory clock interface Memory clock interface Memory clock interface DDR2 SDRAM DDR2 SDRAM DDR SDRAM DDR SDRAM DDR2 SDRAM DDR2 SDRAM DDR SDRAM DDR SDRAM 2.5-V differential signaling 2.5-V differential signaling Differential Altera Corporation September 2008 Table 6–6 ...
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... For more information on I/O availability in HardCopy II devices, refer to the I/O Structures and Features section in volume 1 of the HardCopy Series Handbook. Altera Corporation September 2008 Table 6–7. <value> setting on integer mA, 4 mA, 8 mA, 10 mA, 12 mA, 16 mA, 18 mA, ...
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... Designs not fully constrained would result in significantly different timing characteristics between the prototype Stratix II FPGA and the HardCopy II device. By fully constraining a design, Altera can guarantee that both the Stratix II FPGA and the HardCopy II device fully complies with your timing specifications. ...
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... MHz, but with different clock latency and skew. ## Example TimeQuest SDC Constraints Defining Clocks clk_a and clk_b create_clock -period 10.0 -name clk_a [get_ports clk_a] set_clock_latency -source -late 3.0 clk_a set_clock_latency -source -early 2.0 clk_a Altera Corporation September 2008 Clock settings (F ) for each and every clock domain MAX ...
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... Altera Corporation September 2008 ...
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... Analyzer, feedback from the output to input side of bidirectional I/O, read-while-write paths through memories, and cross-clock domain paths are not timed during optimization or timing analysis. By default, in Time Quest, cross-clock domain paths are timed. Altera Corporation September 2008 [-disable] [-end] [-from <from_list>] \ [-hold] [-remove] [-setup] [-start] \ [-to < ...
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... Don’t care about timing on the resetn net. Set as false path set_false_path -from resetn 6–24 [-from <from list>] \ [-to <to list>] \ [-thru <thru list>] [-comment <comment>] \ [-disable] \ [-from <from_pin_list>] \ [-remove] \ [-to <to_pin_list>] Altera Corporation September 2008 ...
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... Stratix II FPGA prototype design. The execute_flow command is provided for this purpose and supports various arguments Prototype affecting the compilation process. The syntax for this command is: Design tcl> execute_flow \ Altera Corporation September 2008 Compiling the Stratix II Prototype Design [-analysis_and_elaboration] \ [-attempt_similar_placement] \ [-check_ios] \ ...
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... Table 6–8. Perform synthesis and mapping to the target Altera technology Runs Attempt Similar Placement Verify I/O assignments Perform syntax checks on the netlist Execute the Quartus II compilation flow As for compile, but also run simulation Runs the early timing estimator ...
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... Design create the HardCopy II version of the design, run the execute_hardcopyii Tcl command with the -create_companion option: tcl> execute_hardcopyii -create_companion demo_design_hcii Altera Corporation September 2008 tcl> execute_flow -analysis_and_elaboration tcl> execute_flow -check_ios tcl> execute_flow -compile puts "\nResult: $result\n" puts "ERROR: Compilation failed. See report files.\n" ...
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... Description Synthesis settings, source files, messages, and resource usage. Implementation equations and device resource instantiations. Fitter settings, layout optimizations, resources, pin-out, and messages. Implemented equations and device resource instantiations after fitting. Design rule settings, violations, and messages. Altera Corporation September 2008 ...
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... Flow <revision>.sta.rpt TimeQuest Comparing Before submitting the HardCopy II project to the Altera Design Center, it should be checked against the Stratix II prototype FPGA revision FPGA and this, run the execute_hardcopyii Tcl command with the -compare option from the quartus_sh shell: HardCopy Revisions tcl> ...
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... Passed (1020/1020) ; Passed (1/1) ; Passed (2/2) ; Passed (3/3) ; Passed (10/10) ; Passed (100/100) ; Passed (8/8) ; Passed (335084/335084) ; Passed (1/1) Use the execute_module -tool sta Tcl command to run a timing analysis Tcl script in quartus_sta from within the basic quartus shell, quartus_sh Altera Corporation September 2008 ...
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... The Tcl script includes all timing constraints applied during the Quartus II software compilation. Altera Corporation September 2008 Run the quartus_sta interactive Tcl shell independently and execute Tcl commands and scripts at the Tcl prompt. Use the execute_module -tool tan Tcl command to run a timing analysis Tcl script in quartus_tan from within the basic quartus shell, quartus_sh ...
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... HardCopy II target revision execute_hardcopyii -create_companion demo_design_hcii project_close project_open demo_design -revision demo_design_hcii ## Compile the HardCopy II design revision execute_flow -compile ## Check the HardCopy II revision and make sure it matches the FPGA ## design execute_hardcopyii -compare 6–32 Altera Corporation September 2008 ...
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... DEVICE EP2S90F1020C4 set_global_assignment -name TOP_LEVEL_ENTITY demo_design ## HardCopy II Companion Revision and Target Settings ## ================================================== set_global_assignment -name COMPANION_REVISION_NAME \ demo_design_hardcopyii set_global_assignment -name DEVICE_TECHNOLOGY_MIGRATION_LIST HC230F1020 ## Design Assistant Assignments and Settings Required for HardCopy II ## ================================================================== set_global_assignment -name ENABLE_DRC_SETTINGS ON set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name REPORT_IO_PATHS_SEPARATELY ON ## The following assignments are Classic Timing Analyzer only and ## are not used by TimeQuest ...
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... MHz -name ref_clk [get_ports ref_clk] set_clock_latency -late 3 ref_clk set_clock_latency -early 2 ref_clk set_clock_uncertainty –hold –to ref_clk 0.250 set_clock_uncertainty –setup –to ref_clk 0.250 # Input delay of 6ns (max) & 2ns (min) for bus data_in[1:0] set_input_delay –clock ref_clk –max 6 [get_ports data_in] 6–34 Altera Corporation September 2008 ...
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... This chapter introduced script-based design for HardCopy II devices using the Quartus II interactive Tcl shell. This approach provides you with an alternative to GUI-based design for certain situations such as remote-terminal Quartus II execution, design flow automation, or even if you are simply more comfortable operating in a scripting environment. Altera Corporation September 2008 Summary 6–35 ...
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... October 2005 v1.0 Initial release of Script-Based Design for Hardcopy II Devices. 6–36 shows the revision history for this chapter. Changes Made Summary of Changes — — A medium update to the chapter, due to changes in the Quartus II software version 6.1 release. — — Altera Corporation September 2008 ...
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... HardCopy II design flow will soon be mandatory. The TimeQuest timing analyzer is a complete static timing analysis tool that you can use as a sign-off tool for Altera FPGAs and structured ASICs. As FPGA devices become denser and faster, they are the targets of complex designs and applications that previously were implemented in ASICs ...
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... Coarse-grain adaptive logic modules (ALMs) in Stratix II devices are mapped to fine-grain HCell macros in HardCopy II devices Design connections are implemented using custom metal routing in HardCopy II devices HardCopy II devices contain no SRAM-configurable programmable connection points Leaf sub-trees in HardCopy II global clock networks are custom routed Altera Corporation September 2008 ...
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... RAM-block access time is similar in a Stratix II FPGA and its corresponding HardCopy II device. However, as for DSP functions, the timing performance of paths between the RAM blocks and other core logic is generally faster in the HardCopy II device than in the Stratix II FPGA. Altera Corporation September 2008 Introduction 7–3 ...
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... Reduced die-size means shorter overall clock tree routing length Leaf sub-trees of clock networks are custom routed using customized metal mask layers Clock tree latency and clock insertion delay Clock skew Clock jitter PLL compensation delays “Internal Register-to-Register “Clock Distribution Effects” Altera Corporation September 2008 ...
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... HardCopy II timing closure methodology is comprehensive and includes both the TimeQuest timing analyzer and Classic Timing Analyzer in the Quartus II software, an interface to a third-party static timing analyzer, and FPGA-prototype timing verification in the hardware. Altera Corporation September 2008 HardCopy II Timing Closure Methodology “Clock Distribution Effects” ...
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... HardCopy Series Handbook, Volume 1 Altera recommends you use the TimeQuest timing analyzer. You can specify that the TimeQuest timing analyzer be used by the Quartus II software rather than the default Classic Timing Analyzer. The TimeQuest timing analyzer validates the timing performance of all logic in your design using an industry-standard constraint, analysis, and reporting methodology ...
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... In addition, the timing constraint checkers in both TimeQuest and Classic Timing Analyzer report the unconstrained timing paths. See details. For timing verification in third-party tools, the Quartus II Altera Corporation September 2008 HardCopy II Timing Closure Methodology Note (1) Stratix II Revision ...
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... Tcl Packages and Commands chapter of the Quartus II Scripting Reference Manual. Using the TimeQuest Timing Analyzer The TimeQuest timing analyzer plays an integral part in the Quartus II HardCopy II timing closure flow, from the specification of timing constraints to the verification of design requirements. 7–8 Altera Corporation September 2008 ...
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... Tcl packages in the Quartus II software. These packages are the sdc package and the sdc_ext package. The HardCopy II design flow requires that all timing constraints be specified in commands from the SDC Version 1.5 Altera Corporation September 2008 HardCopy II Timing Closure Methodology Figure 7– ...
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... SDC and TimeQuest API Reference Manual. In addition to these timing-related checks, you should review the Quartus II timing report sections in the Compilation Report and resolve any timing violations that may be reported Figure 7–3. TimeQuest Unconstrained Timing Path Report 7–10 (Figure 7–3). Altera Corporation September 2008 ...
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... CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS to OFF. Otherwise, the unconstrained path report (UCP report) will list all clock domain crossing paths as unconstrained. The report does not honor the ON setting, which cuts timing from clocks not originating from the same PLL. Altera Corporation September 2008 HardCopy II Timing Closure Methodology (Figure 7– ...
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... HardCopy II design to the HCDC. Failure to remove these incompatible constraints may result in delays during back-end timing closure. 7–12 ( Figure 7–5) together list all the timing “Unsupported HardCopy II Timing 7–21. Altera Corporation September 2008 ...
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... Figure 7–5. Classic Timing Analyzer Unsupported Timing Assignments in HardCopy II Advisor Altera Corporation September 2008 HardCopy II Timing Closure Methodology 7–13 ...
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... FPGA implementation, must also be used for the HardCopy Devices implementation. If you did not use timing constraints or you used only partial timing constraints for the design, you must add constraints to 7–14 7–6). This section reports all unconstrained paths based on the Altera Corporation September 2008 ...
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... Clock parameters that must be defined are frequency, time at which the clock edge rises, time at which the clock edge falls, clock uncertainty (for example: jitter, noise, and designed in timing margin), and clock name. Altera Corporation September 2008 Constraining Timing of HardCopy Series Devices Clock definitions ...
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... Rising Edge Falling Edge of Clock of Clock Consult with your Altera Field Applications Engineer (FAE) or use MySupport regarding PLL clock uncertainty calculation for your design. Although derive_pll_clocks is in the sdc_ext package the unique exception to the requirement that all timing constraints in the HardCopy II design flow must be in the sdc package ...
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... Figure 7–9 which may be different for each clock domain. You may specify the minimum on-chip delay from any primary input port to describe input hold-time requirements. Altera Corporation September 2008 Constraining Timing of HardCopy Series Devices Figure 7–8 shows the external timing constraint that ...
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... There are two ways to capture the output port timing, as described in the following two sections. 7–18 tsu for a Primary Input Port Data Path Delay shows a generic circuit with an on-chip hold-time constraint. tH for a Primary Input Data Path Delay tsu Clock Delay tH Clock Delay Altera Corporation September 2008 ...
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... Figure 7–12. On-Chip Clock-to-Output (T clk Altera Corporation September 2008 Constraining Timing of HardCopy Series Devices Figure 7–11 Primary Output from Data Path D Q ...
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... After capturing the information, the Altera HCDC directly checks all timing of the HardCopy series device before tape-out occurs. If any timing violations occur in the HardCopy series device due to overly aggressive timing constraints, Altera must fix them, or you must waive them. 7–20 Figure 7–13 ...
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... For this reason, Altera recommends that you use timing constraints in the industry-standard SDC format with the TimeQuest timing analyzer or use only supported timing constraints for Classic Timing Analyzer from the start of your HardCopy II project ...
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... Quartus II software and subsequent transfer to the Altera HardCopy Design Center for the back-end design of your structured ASIC. Following the recommendations in this chapter will help ensure success in your HardCopy II project. 7– ...
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... Updated “HardCopy II Timing Closure Methodology” section. ● Added revision history. March 2006, v1.0 Added document to the HardCopy Series Handbook. Altera Corporation September 2008 shows the revision history for this chapter. Changes Made Document Revision History Summary of Changes — — ...
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... HardCopy Series Handbook, Volume 1 7–24 Altera Corporation September 2008 ...
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... Stratix II and HardCopy II companion device pair or any resource differences between Stratix II devices and the HardCopy II device. This document includes the following topics: ■ ■ ■ ■ ■ ■ Altera Corporation September 2008 8. Migrating Stratix II Device Resources to HardCopy II ® ® HardCopy II devices and Stratix Stratix II and HardCopy II Migration Options ...
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... Global and Local Signals Stratix II ALM Adaptation into HardCopy II Logic HardCopy II DSP Implementation from Stratix II DSP Blocks JTAG BST and Extended Functions Power Up and Configuration Compatibility shows vertical migration options by package. ® package, the Quartus II software Altera Corporation September 2008 ...
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... Table 8–1: (1) Table 8–1 does not include the HC210W device. For information on the HC210W device, contact the Altera Applications Group. (2) This is a Hybrid FineLine BGA package. For more details, refer to the Package Information for Stratix II Devices chapter in volume 2 of the Stratix Device Handbook. ...
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... Table 8–2 does not include the HC210W device. For information on the HC210W device, contact the Altera Applications Group. This is a Hybrid FineLine BGA package. For more details, refer to the Package Information for Stratix II Devices chapter in volume 2 of the Stratix Device Handbook. ...
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... Table 8–3: (1) Table 8–3 does not include the HC210W device. For information on the HC210W device, contact the Altera Applications Group. (2) ALM: adaptive logic module. User I/O pin counts are preliminary. The Quartus II software I/O pin counts include one additional pin, PLL_ENA, (3) which is not included in this pin count ...
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... PCI clamping circuitry to support the PCI interface on HardCopy II devices. 8–6 HC220 HC230 672-Pin 780-Pin 1,020-Pin FineLine BGA FineLine BGA 492 494 494 Notes (3) HC240 (4) 1,020-Pin 1,508-Pin FineLine BGA FineLine BGA 698 698 698 742 951 ) type I/O REF I/O REF Altera Corporation September 2008 (1), ...
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... HC210 and HC220 but memory interface IOEs on HC230 and HC240 devices. The general purpose IOEs on the bottom of the device support PCI clamping, but the general purpose IOEs on the right side do not. Altera Corporation September 2008 I/O Support and Planning Figure 8–1 8– ...
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... SSTL and differential HSTL I/O standards. PLL 12 PLL 6 Bank 8 Memory Interface IOEs Bank 12 Bank 10 “Differential I/O Termination” on page 8–20 REF Bank 4 PLL 10 Bank 5 High-Speed IOEs PLL 4 PLL 3 Bank 6 High-Speed IOEs Bank 7 PLL 9 for more details. pins. Altera Corporation September 2008 ...
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... Table 8–6. Hardcopy II Supported I/O Standards on User I/O Pins (Part I/O Standard 3.3-V LVTTL/LVCMOS Single-ended 2.5-V LVTTL/LVCMOS Single-ended 1.8-V LVTTL/LVCMOS Single-ended 1.5-V LVCMOS Single-ended Altera Corporation September 2008 lists the maximum I/O count per IOE type. This helps you Notes Memory Interface General Purpose IOEs Top Bottom Right ...
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... Memory General High- Interface Purpose Speed IOEs IOEs IOEs (1) (2) (2) (2) (2) (2) 1.8/1.5 (2) (2) ( Altera Corporation September 2008 ...
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... SSTL-2 class I differential and II output (6) Differential Pseudo 3.3/2.5/ SSTL-18 class I differential 1.8/1.5 (6) and II input Altera Corporation September 2008 lists the I/O standards that HardCopy II devices support. is organized by clock input, clock output, and PLL feedback Level (V) CLK[4..7, CCIO CLK[0..3, 12..15] 8..11] (1) Input ...
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... Pseudo-differential HSTL and SSTL outputs use two single-ended outputs with the second output programmed as inverted. This is similar to a Stratix II device implementation. (7) This is not supported. 8–12 Level (V) CLK[4..7, CCIO CLK[0..3, 12..15] 8..11] (1) Input Output (2) 1.8 v 1 2.5 2.5 2 2.5V (7) v FPLL_CLK PLL_OUT PLL_FB (3) (4) ( Altera Corporation September 2008 ...