HC230F1020 Altera, HC230F1020 Datasheet - Page 183

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Altera Corporation
September 2008
External Output Delay Specification
One way to capture output port timing is to describe the external timing
environment, which is the maximum and minimum delay times of
external signals that are driven by the primary output ports of the
HardCopy series device.
constraint driven by the primary output port. The static timing analysis
tool uses this information to check that the on-chip timing of the output
signals is within the desired specification.
Figure 7–11. External Timing Constraint for a Primary Output Port
Internal Output Delay (Tco) Specification
This approach describes the acceptable maximum and minimum on-chip
clock-to-output (T
describe the time it takes from the active edge of the clock to the data
arriving at the primary output port.
with an on-chip T
T
Figure 7–12. On-Chip Clock-to-Output (T
clk
CO
requirement.
D
dff
Q
HardCopy Device or FPGA
CO
CO
Data Path
Delay
Clock
Delay
time constraint. In addition, there can be a minimum
) delay. For example, you can use this approach to
tco for a Primary Output Port
Figure 7–11
Constraining Timing of HardCopy Series Devices
Primary Output from
FPGA/HardCopy
Series Device
Figure 7–12
co
shows the external timing
) Time Constraint
tco
External Device
shows a generic circuit
Data Path
Delay
Data
Path
Delay
External Output Delay
D
dff
output
Q
7–19