HC230F1020 Altera, HC230F1020 Datasheet - Page 108

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

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HardCopy Series Handbook, Volume 1
5–16
f
The derive_clock_uncertainty command applies inter-clock,
intra-clock, and I/O interface uncertainties. This command automatically
calculates and applies setup and hold clock uncertainties for each
clock-to-clock transfer found in your design.
In order to get I/O interface uncertainty, you must create a virtual clock,
then assign delays to the input/output ports by using the
set_input_delay and set_output_delay commands for that
virtual clock.
1
The syntax for the derive_clock_uncertainty is as follows:
derive_clock_uncertainty [-h | -help] [-long_help]
[-dtw] [-overwrite]
where the arguments are listed in
When the dtw option is used, a PLLJ_PLLSPE_INFO.txt file is generated.
This file lists the name of the PLLs, as well as their jitter and SPE values
in the design. This text file can be used by HCII_DTW_CU_Calculator.
When this option is used, clock uncertainties are not calculated.
For more information on the derive_clock_uncertainty command,
refer to the Quartus II TimeQuest Timing Analyzer chapter in volume 3 of
the Quartus II Handbook.
-h | -help
-long_help
-dtw
-overwrite
Table 5–2. Arguments for derive_clock_uncertainty
Option
These uncertainties are applied in addition to those you
specified using the set_clock_uncertainty command.
However, if a clock uncertainty assignment for a source and
destination pair was already defined, the new one will be
ignored. In this case, you can use either the -overwrite
command to overwrite the previous clock uncertainty command
or manually remove them by using the
remove_clock_uncertainty command.
Short help
Long help with examples and possible return values
Creates PLLJ_PLLSPE_INFO.txt file
Overwrites previously performed clock uncertainty assignments
Table
Description
5–2:
Altera Corporation
September 2008