HC230F1020 Altera, HC230F1020 Datasheet - Page 19

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Altera Corporation
September 2008
Note to
(1)
(2)
(3)
(4)
HC210W
HC210
Table 2–4. HardCopy II Embedded Memory Features
Table 2–6. HardCopy II PLLs Available (Part 1 of 2)
Device
Maximum performance information is preliminary until device characterization.
The memory cells power up randomly, so reads before writes are not valid. Make sure you write to the memory
location before you read it.
Even though the output register is cleared, the memory cells power up randomly. So reads before write are not
valid. Make sure you write to the memory location first before reading it.
Violating the setup or hold time requirements on the address registers could corrupt the memory contents. This
applies to both read and write operations.
Table
2–4:
Feature
v
v
1
v
v
2
Enhanced and Fast PLLs
The number of PLLs available differs based on density
The target HardCopy II device may not support the same number of
enhanced PLLs as the prototyping Stratix II FPGA. However, since
HardCopy II enhanced PLLs and fast PLLs offer a similar feature set
(Table 2–7 on page
PLL. The type of PLL used in the design should be chosen using the
Quartus II software to accommodate the resources available in the
HardCopy II device.
Table 2–6
Figure 2–3
using the FPGA, you must select the appropriate number of enhanced
and fast PLLs that will be used in your HardCopy II device. Use
to ensure that the FPGA prototyping design uses the same PLL resources
available in the HardCopy II device.
Enhanced PLLs
Fast PLLs
Table 2–5. HardCopy II PLLs
3
Feature
Fast PLLs
4
shows which PLLs are available in each device density.
shows the location of each PLL. During the prototyping stage
7
HC210W
M4K Blocks
2–13), a fast PLL could be used in place of an enhanced
2
2
8
(Part 2 of 2)
Note (1)
HC210
9
2
2
Notes
10
HC220
(1), (2),
2
2
v
v
5
PLLs and Clock Networks
M-RAM Blocks
(3)
Enhanced PLLs
HC230
v
v
6
(Table
4
4
11
Preliminary
2–5).
Table 2–6
HC240
4
8
2–11
12