HC230F1020 Altera, HC230F1020 Datasheet - Page 31

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Altera Corporation
September 2008
HC210W
HC210
HC220
HC230
Table 2–11. DQS and DQ Bus Mode Support (Part 1 of 2)
Device
484-pin FineLine BGA
(Wire Bond)
484-pin FineLine BGA
672-pin FineLine BGA
780-pin FineLine BGA
1,020-pin FineLine BGA
Package
■
■
■
■
The memory interface DQS, CLK, and PLL_FB input pins and the
PLL_OUT output pins support the following I/O standards:
■
■
■
■
■
■
■
■
■
■
■
■
Pseudo-differential HSTL and SSTL inputs are supported on clock and
DQS pins, while outputs are supported on dedicated PLL_OUT and DQS
pins. Pseudo-differential HSTL and SSTL I/O standards use two
single-ended outputs with the second output programmed as inverted.
Pseudo-differential HSTL and SSTL inputs treat differential inputs as two
single-ended HSTL and SSTL inputs and only decode one of them. This
I/O support is the same as in Stratix II FPGAs.
The functionality of all DQS circuitry in HardCopy II devices is the same
as in Stratix II FPGAs.
supported in each HardCopy II device density and package.
SSTL-2 class I and II
SSTL-18 class I and II
1.8-V HSTL class I and II
1.5-V HSTL class I and II
LVTTL/LVCMOS
SSTL-2 class I and II
SSTL-18 class I and II
1.8-V HSTL class I and II
1.5-V HSTL class I and II
Differential SSTL-2 class I and II
Differential SSTL-18 class I and II
1.8-V differential HSTL class I and II
1.5-V differential HSTL class I and II
LVDS (not supported on DQS pins)
HyperTransport technology (not supported on DQS pins)
LVPECL on input clocks and PLL_OUT only (not supported on DQS
pins)
Number of ×4
Groups
36
4
4
9
9
Table 2–11
Number of ×8/×9
Groups
18
2
2
4
4
shows the number of DQS/DQ groups
×16/×18 Groups
Number of
I/O Structure and Features
0
0
2
2
8
×32/×36 Groups
Number of
Preliminary
0
0
0
0
4
2–23