HC230F1020 Altera, HC230F1020 Datasheet - Page 88

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

HardCopy Series Handbook, Volume 1
Electrostatic
Discharge
4–46
In a hot socketing situation, a device’s output buffers are turned off
during system power-up or power-down. To simplify board design,
HardCopy II devices support any power-up or power-down sequence
(V
signals into the device before or during power-up or power-down
without damaging the device.
You can power up or power down the V
sequence. The power supply ramp rates can range from 100 ns to 100 ms.
All VCC supplies must power down within 100 ms of each other to
prevent the I/O pins from driving out. During hot socketing, the I/O pin
capacitance is less than 15 pF and the clock pin capacitance is less than
20 pF.
■
■
1
Electrostatic discharge (ESD) protection is a design practice that is
integrated in Altera FPGAs and structured ASIC devices. HardCopy II
devices are no exception, and they are designed with ESD protection on
all I/O and power pins.
CCIO
The hot socketing DC specification is | I
The hot socketing AC specification is | I
or less.
and V
The DC specification applies when all VCC supplies to the
device are stable in the powered-up or powered-down
conditions. The AC specification applies when the device is
being powered up or powered down in any of the conditions
mentioned above.
CCINT
). For mixed-voltage environments, you can drive
CCIO
and V
IOPIN
IOPIN
| < 300 µA.
| < 8 mA for 10 ns
CCINT
Altera Corporation
pins in any
September 2008