HC230F1020 Altera, HC230F1020 Datasheet - Page 51

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Altera Corporation
September 2008
Notes to
(1)
(2)
V
V
V
V
V
R
V
V
to-peak)
V
V
V
Table 4–11. 3.3-V LVDS I/O Specifications
Table 4–12. LVPECL Specifications (Part 1 of 2)
Symbol
CCIO
ID
ICM
OD
OCM
CCIO
ID
ICM
OD
OCM
L
Symbol
(peak-
Like Stratix II devices, 3.3-V LVDS is supported by the top and bottom clock input differential buffers, and by the
PLL clock output and feedback pins.
The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V
The PLL clock output and feedback differential buffers are powered by VCC_PLLOUT. For differential clock output
and feedback operation, connect VCC_PLLOUT to 3.3 V.
Table
Output and feedback pins in PLL
banks 9, 10, 11, and 12
Input differential voltage swing
(single-ended)
Input common mode voltage
Output differential voltage
(single-ended)
Output common mode voltage
Receiver differential input discrete
resistor (external to HardCopy II
devices)
I/O supply voltage for I/O
banks that support high-
speed IOEs
Input differential voltage
swing
(single-ended)
Input common mode
voltage
Output differential voltage
(single-ended)
Output common mode
voltage
4–11:
Parameter
Parameter
(2)
(2)
R
R
R
L
L
L
Conditions
= 100 Ω
= 100 Ω
= 100 Ω
Note (1)
—
—
Conditions
R
R
L
L
= 100 Ω
= 100 Ω
Note (1)
—
—
—
—
Minimum
3.135
1.650
300
525
1.0
Minimum
3.135
0.84
100
200
250
90
Typical
Typical
600
1,250
3.3
—
—
—
350
100
3.3
I/O Standard Specifications
—
—
Maximum
Maximum
3.465
1,800
1.570
3.465
1,000
2.275
CCINT
900
710
110
970
2.5
, not V
CCIO
Unit
Unit
mV
mV
mV
mV
mV
mV
V
V
Ω
V
V
4–9
.