72T7285L4-4BBG Integrated Device Technology (Idt), 72T7285L4-4BBG Datasheet
72T7285L4-4BBG
Specifications of 72T7285L4-4BBG
Related parts for 72T7285L4-4BBG
72T7285L4-4BBG Summary of contents
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VOLT HIGH-SPEED TeraSync 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 FEATURES: • • • • • Choose among the following memory organizations: ⎯ ⎯ ⎯ ⎯ ⎯ IDT72T7285 16,384 x 72 ⎯ ⎯ ⎯ ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 PIN CONFIGURATION A1 BALL PAD CORNER A V D60 D61 D63 D66 CC B D59 D58 D62 D64 D67 ...
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DESCRIPTION: The IDT72T7285/72T7295/72T72105/72T72115 are exceptionally deep, extremely high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x72/x36/x18 data flow. These FIFOs ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 DESCRIPTION (CONTINUED) The device can be configured with different input and output bus widths as shown in Table 1. ...
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WRITE CLOCK (WCLK/WR) WRITE ENABLE (WEN) WRITE CHIP SELECT (WCS) (x72, x36, x18) DATA IN (D SERIAL CLOCK (SCLK) SERIAL ENABLE(SEN) FIRST WORD FALL THROUGH/ SERIAL INPUT (FWFT/SI) ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 PIN DESCRIPTION Symbol Name I/O TYPE (1) ASYR Asynchronous LVTTL Read Port INPUT ASYW (1) Asynchronous LVTTL Write Port ...
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PIN DESCRIPTION (CONTINUED) Symbol Name I/O TYPE PAE HSTL-LVTTL PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 PIN DESCRIPTION (CONTINUED) Symbol Name I/O TYPE TRST HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. ...
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ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage Temperature STG I DC Output Current OUT NOTES: 1. Stresses greater than those ...
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... Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order. (1) — SYNCHRONOUS TIMING = 2.5V ± 5 -40°C to +85° Commercial Com’l & Ind’l IDT72T7285L4-4 IDT72T7285L5 IDT72T7295L4-4 IDT72T7295L5 IDT72T72105L4-4 IDT72T72105L5 IDT72T72105L6-7 IDT72T72105L10 IDT72T72115L4-4 IDT72T72115L5 IDT72T72115L6-7 IDT72T72115L10 Min ...
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... Values guaranteed by design, not currently tested. 2. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order. = 2.5V ± 5 -40°C to +85° Commercial IDT72T7285L4-4 IDT72T7295L4-4 IDT72T72105L4-4 IDT72T72115L4-4 Min. Max. — ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 HSTL 1.5V AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels NOTE: ...
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OUTPUT ENABLE & DISABLE TIMING Output Enable OE Output V CC Normally 2 LOW Output V CC Normally 2 HIGH NOTES: 1. REN is HIGH. 2. RCS is ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 FUNCTIONAL DESCRIPTION TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH (FWFT) MODE The IDT72T7285/72T7295/72T72105/72T72115 support two different timing ...
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TABLE 2 — DEFAULT PROGRAMMABLE FLAG OFFSETS IDT72T7285,72T7295,72T72105,72T72115 *LD FSEL1 FSEL0 *LD ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 TABLE 3 ⎯ STATUS FLAGS FOR IDT STANDARD MODE IDT72T7285 0 Number of ( Words in ...
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LD WEN REN NOTES: 1. The programming method can only be selected ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 1st Parallel Offset Write/Read Cycle D/Q71 D/Q19 D/Q17 2nd Parallel Offset Write/Read Cycle D/Q71 D/Q19 D/Q17 ...
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SERIAL PROGRAMMING MODE If Serial Programming mode has been selected, as described above, then programming of PAE and PAF values can be achieved by using a combination of ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 Once a marked location has been set (and the device is still in retransmit mode, MARK is HIGH), a ...
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SIGNAL DESCRIPTION INPUTS: DATA Data inputs for 72-bit wide data ( data inputs for 36-bit wide data 0 ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 marked location. During retransmit mode write operations to the device may continue without hindrance. FIRST WORD FALL THROUGH/SERIAL IN ...
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During Master or a Partial Reset the OE is the only input that can place the output bus Qn, into High-Impedance. During Reset ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 OUTPUTS: FULL FLAG ( FF/IR ) This is a dual purpose pin. In IDT Standard mode, the Full Flag ...
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ECHO READ CLOCK (ERCLK) The Echo Read Clock output is provided in both HSTL and LVTTL mode, selectable via RHSTL. The ERCLK is a free-running clock output, it ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT ...
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BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT BYTE ORDER ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 JTAG TIMING SPECIFICATION t 1 TCK t 3 TDI/ TMS TDO t TRST t 5 SYSTEM INTERFACE PARAMETERS Parameter ...
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JTAG INTERFACE Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72T7285/72T7295/ 72T72105/72T72115 incorporates the necessary tap controller ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 Input = TMS NOTES: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. ...
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THE INSTRUCTION REGISTER The Instruction register allows an instruction to be shifted in serially into the processor at the rising edge of TCLK. The Instruction is used to ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 MRS t RSS REN t RSS WEN t RSS FWFT/SI t RSS LD t RSS FSEL0, FSEL1 t RSS ...
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PRS t RSS REN t RSS WEN t RSS RT t RSS SEN EF/OR FF/IR PAE PAF NOTE: 1. During Partial ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t t ENS ENH ...
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RCLK t ENS REN t ENS t ENH RCS RCSLZ LAST DATA WCLK WEN Dn NOTES: is the minimum time between ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 COMMERCIAL AND INDUSTRIAL 36 TEMPERATURE RANGES ...
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COMMERCIAL AND INDUSTRIAL 37 TEMPERATURE RANGES ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 COMMERCIAL AND INDUSTRIAL 38 TEMPERATURE RANGES ...
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COMMERCIAL AND INDUSTRIAL 39 TEMPERATURE RANGES ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 COMMERCIAL AND INDUSTRIAL 40 TEMPERATURE RANGES ...
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COMMERCIAL AND INDUSTRIAL 41 TEMPERATURE RANGES ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 SCLK t t SCKH SCKL SCLK t t SENS SEN t t LDS LD t SDS BIT 1 ...
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CLKL CLKL WCLK t t ENS ENH WEN PAF +1) words in FIFO RCLK REN NOTES PAF offset ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 WCLK WEN PAF words in FIFO RCLK REN NOTES PAF offset. ...
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WCLK WEN HF D/2 words in FIFO D RCLK REN NOTES IDT Standard mode maximum FIFO depth 16,384 ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 COMMERCIAL AND INDUSTRIAL 46 TEMPERATURE RANGES ...
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WCLK t ENS WEN n+1 n+2 t SKEW1 RCLK a t ERCLK ERCLK REN RCS EREN HIGH-Z ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 RCLK REN FFA NOTE LOW, ...
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No Write WCLK 1 WEN SKEW t CYL Last Word W X NOTE LOW, RCS = LOW and ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 CYC t t CYH CYL Last Word in O/P Register ...
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OPTIONAL CONFIGURATIONS WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from any one ...
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IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 FWFT/SI FWFT/SI WRITE CLOCK WCLK WRITE ENABLE IDT WEN 72T7285 72T7295 INPUT READY IR 72T72105 72T72115 n DATA IN ...
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ORDERING INFORMATION XXXXX X XX Device Type Power Speed Package NOTES: 1. Industrial temperature range product for 5ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Green parts available. For ...