72T7285L4-4BBG Integrated Device Technology (Idt), 72T7285L4-4BBG Datasheet - Page 42

• Manufacturer Part Number: 72T7285L4-4BBG
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 72 324-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T7285L4-4BBG

• Package: 324BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 1.125 Mb
• Organization: 16Kx72
• Data Bus Width: 72 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: 0 to 70 °C

NOTE:
1. X = 14 for the IDT72T7285, X = 15 for the IDT72T7295, X = 16 for the IDT72T72105, X = 17 for the IDT72T72115.
NOTE:
1. This timing diagram illustrates programming with an input bus width of 72 bits.
NOTES:
1. OE = LOW; RCS = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 72 bits.
3. The offset registers cannot be read on consecutive RCLK cycles. The read must be disabled (REN = HIGH) for a minimum of one RCLK cycle in between register accesses.
SCLK
D
Q
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
WCLK
RCLK
0
0
SEN
WEN
REN
- Q
LD
- D
LD
LD
SI
n
n
DATA IN OUTPUT REGISTER
t
SCKH
t
CLKH
t
Figure 21. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
SCLK
Figure 20. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
Figure 22. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
CLK
t
t
SCKL
SENS
t
t
LDS
SDS
BIT 1
t
CLKL
t
LDS
t
ENS
t
t
LDS
t
SENH
A
t
t
CLKH
LDH
t
ENH
EMPTY OFFSET
t
CLK
t
t
t
ENS
LDS
t
CLKL
DS
PAE OFFSET VALUE
OFFSET
PAE
BIT X
(1)
42
t
ENH
t
t
LDH
DH
t
LDS
t
ENS
BIT 1
t
A
t
LDH
t
ENH
OFFSET
PAF
t
t
LDH
ENH
FULL OFFSET
t
DH
PAF OFFSET VALUE
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
BIT X
t
LDS
t
ENS
t
t
(1)
ENH
t
SDH
LDH
t
A
t
LDH
t
ENH
PAE OFFSET
5994 drw27
5994 drw25
5994 drw26