72T7285L4-4BBG Integrated Device Technology (Idt), 72T7285L4-4BBG Datasheet - Page 6

• Manufacturer Part Number: 72T7285L4-4BBG
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 72 324-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T7285L4-4BBG

• Package: 324BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 1.125 Mb
• Organization: 16Kx72
• Data Bus Width: 72 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: 0 to 70 °C

PIN DESCRIPTION
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
Symbol
ASYR
ASYW
BE
BM
D
EF/OR
ERCLK RCLK Echo
EREN
FF/IR
FSEL0
FSEL1
FWFT/
HF
IP
IW
LD
MARK
MRS
OE
OW
SI
0
(1)
–D
(1)
(1)
(1)
(1)
71
(1)
(1)
(1)
(1)
Asynchronous
Read Port
Asynchronous
Write Port
Big-Endian/
Little-Endian
Bus-Matching
Data Inputs
Empty Flag/
Output Ready
Read Enable Echo HSTL-LVTTL Read Enable Echo output, only available when the Read is setup for Synchronous mode.
Full Flag/
Input Ready
Flag Select Bit 0
Flag Select Bit 1
First Word Fall
Through/Serial In
Half-Full Flag
Interspersed Parity
Input Width
Load
Mark for Retransmit HSTL-LVTTL When this pin is asserted the current location of the read pointer will be marked. Any subsequent Retransmit
Master Reset
Output Enable
Output Width
Name
HSTL-LVTTL Data inputs for a 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, the unused input pins are in a don’t care
HSTL-LVTTL In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty.
HSTL-LVTTL Read clock Echo output, only available when the Read is setup for Synchronous mode.
HSTL-LVTTL In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is
HSTL-LVTTL During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin
HSTL-LVTTL HF indicates whether the FIFO memory is more or less than half-full.
HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1,
HSTL-LVTTL MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master
HSTL-LVTTL OE provides Asynchronous three-state control of the data outputs, Q
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
INPUT
LVTTL
INPUT
LVTTL
INPUT
INPUT
LVTTL
INPUT
LVTTL
INPUT
INPUT
INPUT
INPUT
INPUT
LVTTL
INPUT
I/O TYPE
will select Asynchronous operation.
programmable flags PAE and PAF. There are up to eight possible settings available.
programmable flags PAE and PAF. There are up to eight possible settings available.
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed
operation will reset the read pointer to this position.
Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations,
A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW
will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode.
A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW
During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset
BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size
configuration.
state.
In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the
outputs.
full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for
writing to the FIFO memory.
During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the
During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the
functions as a serial input for loading offset registers. If Asynchronous operation of the read port has been
selected then the FIFO must be set-up in IDT Standard mode.
Parity mode.
This pin, along with OW and BM, selects the bus width of the write port. See Table 1 for bus size configuration.
determines one of eight default offset values for the PAE and PAF flags, along with the method by which these
offset registers can be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing
to and reading from the offset registers. THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE OR
READ DATA TO/FROM THE FIFO MEMORY.
Synchronous/Asynchronous operation of the read or write port, one of eight programmable flag default settings,
serial or parallel programming of the offset settings, Big-Endian/Little-Endian format, zero latency timing mode,
interspersed parity, and synchronous versus asynchronous programmable flag timing modes.
OE input is the only input that provide High-Impedance control of the data outputs.
This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration.
will select Little-Endian format.
6
Description
COMMERCIAL AND INDUSTRIAL
n.
During a Master or Partial Reset the
TEMPERATURE RANGES