72T7285L4-4BBG Integrated Device Technology (Idt), 72T7285L4-4BBG Datasheet - Page 7

• Manufacturer Part Number: 72T7285L4-4BBG
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 72 324-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T7285L4-4BBG

• Package: 324BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 1.125 Mb
• Organization: 16Kx72
• Data Bus Width: 72 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: 0 to 70 °C

16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
PIN DESCRIPTION (CONTINUED)
Symbol
PAE
PAF
PFM
PRS
Q
RCLK/
RD
RCS
REN
RHSTL
RT
SCLK
SEN
SHSTL
TCK
TDI
TDO
TMS
0
–Q
(2)
(2)
(1)
(2)
(2)
71
(1)
Programmable
Almost-Empty Flag
Programmable
Almost-Full Flag
Programmable
Flag Mode
Partial Reset
Data Outputs
Read Clock/
Read Strobe
Read Chip Select HSTL-LVTTL RCS provides synchronous control of the read port and output impedance of Qn, synchronous to RCLK. During
Read Enable
Read Port HSTL
Select
Retransmit
Serial Clock
Serial Enable
System HSTL
Select
JTAG Clock
JTAG Test Data
Input
JTAG Test Data
Output
JTAG Mode
Select
Name
HSTL-LVTTL PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the
HSTL-LVTTL PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in
HSTL-LVTTL PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,
HSTL-LVTTL Data outputs for an 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, any unused output pins should not
HSTL-LVTTL If Synchronous operation of the read port has been selected, REN enables RCLK for reading data from the
HSTL-LVTTL RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to
HSTL-LVTTL A rising edge on SCLK will clock the serial data present on the SI input into the offset registers providing that
HSTL-LVTTL SEN enables serial loading of programmable flag offsets.
HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations
HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
HSTL-LVTTL If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK
I/O TYPE
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
INPUT
LVTTL
INPUT
INPUT
INPUT
LVTTL
INPUT
INPUT
INPUT
INPUT
LVTTL
Empty Offset register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal
to offset n.
the Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal
to m.
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on
PFM will select Synchronous Programmable flag timing mode.
the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings
are all retained.
be connected. Outputs are not 3.3V tolerant regardless of the state of OE and RCS.
reads data from the FIFO memory and offsets from the programmable registers. If LD is LOW, the values loaded
into the offset registers is output on a rising edge of RCLK. If Asynchronous operation of the read port has
been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be
tied LOW.
a Master Reset or Partial Reset the RCS input is don’t care, if OE is LOW the data outputs will be Low-Impedance
regardless of RCS.
FIFO memory and offset registers. If Asynchronous operation of the read port has been selected, the REN
input should be tied LOW.
This pin is used to select HSTL or 2.5V LVTTL outputs for the FIFO. If HSTL or eHSTL outputs are
required, this input must be tied HIGH. Otherwise it should be tied LOW.
HIGH in FWFT mode) and doesn’t disturb the write pointer, programming method, existing timing mode or
programmable flag settings. If a mark has been set via the MARK input pin, then the read pointer will jump to
the ‘mark’ location.
SEN is enabled.
INPUT
All inputs not associated with the write or read port can be selected for HSTL operation via the SHSTL input.
of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and
outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.
test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register
and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID
Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and
SHIFT-IR controller states.
the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
7
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES