72T7285L4-4BBG Integrated Device Technology (Idt), 72T7285L4-4BBG Datasheet - Page 35

• Manufacturer Part Number: 72T7285L4-4BBG
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 72 324-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T7285L4-4BBG

• Package: 324BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 1.125 Mb
• Organization: 16Kx72
• Data Bus Width: 72 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: 0 to 70 °C

NOTES:
1. t
2. LD = HIGH.
3. First data word latency = t
4. OE is LOW.
Q0 - Qn
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
WCLK
RCLK
rising edge of WCLK and the rising edge of RCLK is less than t
WEN
SKEW1
RCS
REN
Dn
EF
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus t
t
t
ENS
ENS
t
RCSLZ
t
ENH
SKEW1
t
A
+ 1*T
LAST DATA-1
RCLK
Figure 13. Read Cycle and Read Chip Select (IDT Standard Mode)
+ t
REF.
t
RCSHZ
SKEW1
t
ENS
, then EF deassertion may be delayed one extra RCLK cycle.
t
RCSLZ
t
REF
t
35
A
t
t
ENS
DS
LAST DATA
D
t
ENS
x
t
SKEW1
t
ENH
t
DH
(1)
1
t
RCSHZ
COMMERCIAL AND INDUSTRIAL
2
TEMPERATURE RANGES
t
REF
REF
). If the time between the
5994 drw18