72T7285L4-4BBG Integrated Device Technology (Idt), 72T7285L4-4BBG Datasheet - Page 43

• Manufacturer Part Number: 72T7285L4-4BBG
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 72 324-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T7285L4-4BBG

• Package: 324BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 1.125 Mb
• Organization: 16Kx72
• Data Bus Width: 72 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: 0 to 70 °C

NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. t
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
7. RCS = LOW.
WCLK
RCLK
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
WCLK
RCLK
WEN
REN
PAF
WEN
rising edge of WCLK and the rising edge of RCLK is less than t
In IDT Standard mode: D = 16,384 for the IDT72T7285, 32,768 for the IDT72T7295, 65,536 for the IDT72T72105 and 131,072 for the IDT72T72115.
In FWFT mode: D = 16,385 for the IDT72T7285, 32,769 for the IDT72T7295, 65,537 for the IDT72T72105 and 131,073 for the IDT72T72115.
rising edge of RCLK and the rising edge of WCLK is less than t
REN
SKEW2
SKEW2
PAE
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus t
t
CLKH
t
CLKL
Figure 24. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t
ENS
t
ENS
n words in FIFO
n + 1 words in FIFO
t
CLKL
D - (m +1) words in FIFO
t
CLKL
t
ENH
(2)
t
SKEW2
,
1
(3)
t
ENH
(4)
t
PAES
(2)
1
2
SKEW2
SKEW2
, then the PAF deassertion time may be delayed one extra WCLK cycle.
, then the PAE deassertion may be delayed one extra RCLK cycle.
2
43
t
PAFS
t
ENS
t
ENS
n + 1 words in FIFO
n + 2 words in FIFO
t
ENH
t
SKEW2
(3)
t
(2)
ENH
D - m words in FIFO
,
(3)
1
1
COMMERCIAL AND INDUSTRIAL
(2)
t
PAES
TEMPERATURE RANGES
PAES
2
PAFS
2
t
). If the time between the
PAFS
). If the time between the
n words in FIFO
n + 1 words in FIFO
D-(m+1) words
in FIFO
5994 drw29
5994 drw28
(2)
(2)
,
(3)