72T7285L4-4BBG Integrated Device Technology (Idt), 72T7285L4-4BBG Datasheet - Page 15

• Manufacturer Part Number: 72T7285L4-4BBG
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 72 324-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T7285L4-4BBG

• Package: 324BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 1.125 Mb
• Organization: 16Kx72
• Data Bus Width: 72 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: 0 to 70 °C

TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
4. As well as selecting parallel programming mode, one of the default values will
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
be loaded depending on the state of FSEL0 & FSEL1.
also be loaded depending on the state of FSEL0 & FSEL1.
*THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE
OR READ DATA TO/FROM THE FIFO MEMORY.
*LD
*LD
H
H
H
H
H
L
L
L
L
L
IDT72T7285,72T7295,72T72105,72T72115
FSEL1
FSEL1
H
H
H
H
X
X
L
L
L
L
FSEL0
FSEL0
H
H
H
H
X
X
L
L
L
L
Program Mode
Offsets n,m
Parallel
Serial
1,023
255
127
511
63
31
15
7
(3)
(4)
15
PROGRAMMING FLAG OFFSETS
72T7295/72T72105/72T72115 have internal registers for these offsets. There
are eight default offset values selectable during Master Reset. These offset
values are shown in Table 2. Offset values can also be programmed into the
FIFO in one of two ways; serial or parallel loading method. The selection of the
loading method is done using the LD (Load) pin. During Master Reset, the state
of the LD input determines whether serial or parallel flag offset programming is
enabled. A HIGH on LD during Master Reset selects serial loading of offset
values. A LOW on LD during Master Reset selects parallel loading of offset
values.
the current offset values. Offset values can be read via the parallel output port
Q
not possible to read the offset values in serial fashion.
the control pins and sequence for both serial and parallel programming modes.
For a more detailed description, see discussion that follows.
after Master Reset, regardless of whether serial or parallel programming has
been selected. Valid programming ranges are from 0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
the Master Reset cycle with either synchronous or asynchronous timing for PAF
and PAE flags by use of the PFM pin.
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK
only and not WCLK. For detail timing diagrams, see Figure 23 for synchronous
PAF timing and Figure 24 for synchronous PAE timing.
MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE
is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH
on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see
Figure 25 for asynchronous PAF timing and Figure 26 for asynchronous PAE
timing.
0
-Qn, regardless of the programming mode selected (serial or parallel). It is
Full and Empty Flag offset values are user programmable. The IDT72T7285/
In addition to loading offset values into the FIFO, it is also possible to read
Figure 3, Programmable Flag Offset Programming Sequence, summaries
The offset registers may be programmed (and reprogrammed) any time
The IDT72T7285/72T7295/72T72105/72T72115 can be configured during
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES