72T7285L4-4BBG Integrated Device Technology (Idt), 72T7285L4-4BBG Datasheet - Page 8

• Manufacturer Part Number: 72T7285L4-4BBG
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 72 324-Pin BGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72T7285L4-4BBG

• Package: 324BGA
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 1.125 Mb
• Organization: 16Kx72
• Data Bus Width: 72 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 2.5 V
• Operating Temperature: 0 to 70 °C

NOTES:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 29-31 and Figures 6-8.
PIN DESCRIPTION (CONTINUED)
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
Symbol
TRST
WEN
WCS
WCLK/
WR
WHSTL
V
GND
Vref
V
DDQ
CC
(2)
(1)
JTAG Reset
Write Enable
Write Chip Select HSTL-LVTTL This pin disables the write port data inputs when the device write port is configured for HSTL mode. This
Write Clock/
Write Strobe
Write Port HSTL
Select
+2.5v Supply
Ground Pin
Reference
Voltage
O/P Rail Voltage
Name
HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically
HSTL-LVTTL When Synchronous operation of the write port has been selected, WEN enables WCLK for writing data into
HSTL-LVTTL If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK
I/O TYPE
LVTTL
INPUT
INPUT
INPUT
INPUT
INPUT
I
I
I
I
reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles.
If the TAP controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG
function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper
FIFO operation. If the JTAG function is not used then this signal needs to be tied to GND.
the FIFO memory and offset registers. If Asynchronous operation of the write port has been selected, the
WEN input should be tied LOW.
provides added power savings.
writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into
the FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state).
This pin is used to select HSTL or 2.5V LVTTL inputs for the FIFO. If HSTL inputs are required, this input must
be tied HIGH. Otherwise it should be tied LOW.
These are Vcc supply inputs and must be connected to the 2.5V supply rail.
These are Ground pins and must be connected to the GND rail.
This is a Voltage Reference input and must be connected to a voltage level determined from the table,
“Recommended DC Operating Conditions”. This provides the reference voltage when using HSTL class
inputs. If HSTL class inputs are not being used, this pin should be tied LOW.
This pin should be tied to the desired voltage rail for providing power to the output drivers.
8
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES