AM79C875KI AMD (ADVANCED MICRO DEVICES), AM79C875KI Datasheet - Page 10

• Manufacturer Part Number: AM79C875KI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C875KI

• Lead Free Status / RoHS Status: Not Compliant

PIN DESCRIPTIONS
Media Connections
TX[3:0]±
Transmit Output
The TX[3:0]± pins are the differential transmit output
pairs. The TX[3:0]± pins transmit 10BASE-T or MLT-3
signals depending on the state of the link of the port.
RX[3:0]±
Receive Input
The RX[3:0]± pins are the differential receive input
pairs. The RX[3:0]± pins can receive 10BASE-T or
MLT-3 signals depending on the state of the link of the
port.
100BASE-FX Function/Test
SDI+/TEST[0]
Signal Detect Input+
(For Port 3 only)
This pin indicates signal quality status on the fiber-optic
link in 100BASE-FX mode. When the signal quality is
good, the SDI+ pin should be driven high relative to the
SDI- pin. 100BASE-FX is disabled when both pins are
simultaneously pulled low. SDI- can also be used for
Signal Detect Common Mode Voltage input.
When in test mode, SDI+, SDI-, FXR+, and FXR- pins
are used as TEST[3:0].
SDI-/TEST[1]
Signal Detect Input-
(For Port 3 only)
This pin indicates signal quality status on the fiber-optic
link in 100BASE-FX mode. When the signal quality is
good, the SDI+ pin should be driven high relative to the
SDI- pin. 100BASE-FX is disabled when both pins are
simultaneously pulled low. SDI- can also be used for
Signal Detect Common Mode Voltage input.
When in test mode, SDI+, SDI-, FXR+, and FXR- pins
are used as TEST[3:0].
FXR+/TEST[2]
Fiber Receive Input
(For Port 3 only)
When Port 3 is configured as FX Channel, FXR± are
ECL level FX receive pins.
When in test mode, SDI±, and FXR± pins are used as
TEST[3:0].
FXR-/TEST[3]
Fiber Receive Input
(For Port 3 only)
When Port 3 is configured as FX Channel, FXR± are
ECL level FX receive pins.
When in test mode, SDI+, SDI-, FXR+, FXR- pins are
used as TEST[3:0].
10
Analog Input/Output
Analog Input/Output
Analog Input/Output
Analog Input/Output
Output
Input
Am79C875
FXT±
Fiber Transmit Output
(For Port 3 only)
When Port 3 is configured as FX Channel, FXT± are
ECL level FX transmit pins.
Clock
REFCLK
Reference Clock Input Signal
The REFCLK pin is the reference clock input. The
REFCLK signal must be a 50-MHz signal.
RMII Signals
TXD[3:0]_[1:0]
RMII TXD for Ports 0 to 3
These pins are the transmit data input to the RMII of
Ports 0:3.
TX_EN[3:0]
RMII Transmit Enable
These pins are the transmit enable inputs to the RMII.
RXD[3:0]_[1:0]
RMII Receive Data for Ports 0 to 3
These pins are the receive data for Port 0:3.
RX_ER[2:0]
RMII Receive Error for Ports 0 to 2
These pins indicate receive errors for the correspond-
i n g p o r t . T h e p i n g o e s H I G H w h e n e v e r t h e
corresponding receiver detects a symbol error.
RX_ER[3]/PHYAD_ST
RMII Receive Error for Port 3
PHY Address Shift
This pin indicates receive errors for Port 3. It goes
HIGH when the corresponding receiver detects a
symbol error.
At power up, this pin is used to set the PHY address by
increasing it by 1. If it is HIGH at power up, the PHYAD
of each port is the upper-3 bits and the port number for
the lower-2 bits. If it is LOW, the PHYAD is incremented
by 1. For example, if the pin is HIGH at power-up and
the upper-3 bits are set to 000, the PHYAD of each port
(in binary notation) is 00000, 00001, 00010, 00011 re-
spectively. If the pin is LOW at power-up and the upper-
3 bits are set to 000, the PHYAD of each port is 00001,
00010, 00011, and 00100, respectively. This allows a
method of avoiding setting an address to 00000, which
could cause problems with some MACs.
CRS_DV[3:0]
Carrier Sense/Data Valid
The CRS_DV pin is asserted high when media is
non-idle.
Input/Output, Pull-Down
Analog Output
Input/Output
Output
Output
Input
Input
Input