AM79C875KI AMD (ADVANCED MICRO DEVICES), AM79C875KI Datasheet - Page 20

• Manufacturer Part Number: AM79C875KI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C875KI

• Lead Free Status / RoHS Status: Not Compliant

mode filtering blocks the DC component of the code
and the DC offset of the differential receive input can
wander. The shift in the signal levels causes increase
in error rates. A DC restoration circuit is needed to
compensate for the attenuation of DC components.
The NetPHY™ 4LP device implemented a patent-
pending DC restoration circuit which, unlike the tra-
ditional implementation, does not need the feedback
information from the slicer and clock recovery. The
baseline wander correction circuit is not required and,
therefore, is bypassed when the port is 10BASE-T.
Clock/Data Recovery
The equalized MLT-3 signal is converted into NRZI for-
mat. The NetPHY™ 4LP device uses an analog phase
locked loop (APLL) to extract clock information of the
incoming NRZI data which is used to re-time the data
stream and set data boundaries. The receive clocks
are locked to the incoming data streams. PPM should
be between 50 and 100.
20
Notes:
2. The isolation transformers include common-mode chokes.
3. Consult magnetics vendors for appropriate termination schemes.
4. 50 Ω if a 1:1 isolation transformer is used or 78 Ω if a 1.25:1 isolation transformer is used.
5. 50 (49.9) Ω is normal, but 54.9 Ω can be used for extended cable length operation.
SDI/MLT3EN
Figure 7. TX± and RX± Termination for 100BASE-TX and 10BASE-T
RX+
RX–
TX+
TX–
(Note 3)
0.1 µF
1 k
50
50
(Note 3)
Ω
Ω
Ω (Note 4)
(Note 4)
V
DD
0.1 µF
0.1 µF
*
Transformer with
common-mode
1:1 or 1.25:1 *
*
Isolation
chokes
Am79C875
1:1
*
(chassis ground)
75
When initial lock is achieved, the APLL switches to
lock-to-data stream, extracts a 125-MHz clock. The re-
covered 125 MHz clock is also used to generate the 25-
MHz RX_CLK. The APLL requires no external compo-
nents for its operation and has high noise immunity and
low jitter. It provides fast phase align (lock) to data in
one transition and its data/clock acquisition time after
power-on is less than 60 transitions.
The APLL can maintain lock on run-lengths of up to 60
data bits in the absence of signal transitions. When no
valid data is present, the APLL switches back to lock
with the TX_CLK, providing a continuously running
RX_CLK.
The recovered data is converted from NRZI-to-NRZ
and then to a 5-bit parallel format. The 5-bit parallel
data is not necessarily aligned to 4B/5B code-group’s
symbol boundary. The data is presented to PCS at re-
ceive data register output, gated by the 25-MHz
RX_CLK.
Ω
75
Ω
470 pF
75
Ω
(chassis ground)
75
Ω
470 pF
(8)
(7)
TX+ (1)
(5)
(4)
TX– (2)
RX+ (3)
RX– (6)
Connector
RJ45
22236G-9