AM79C875KI AMD (ADVANCED MICRO DEVICES), AM79C875KI Datasheet - Page 18

• Manufacturer Part Number: AM79C875KI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C875KI

• Lead Free Status / RoHS Status: Not Compliant

The 10BASE-T block consists of the following
sub-blocks:
Refer to Figure 5 for the 10BASE-T transmit and
receive data paths.
Figure 5. 10BASE-T Transmit/Receive Data Paths
Twisted Pair Transmit Function
Data transmission over the 10BASE-T medium re-
quires use of the integrated 10BASE-T MAU and uses
the differential driver circuitry on the TX± pins.
TX± is a differential twisted-pair driver. When properly
terminated, TX± meets the transmitter electrical re-
quirements for 10BASE-T transmitters as specified in
IEEE 802.3, Section 14.3.1.2. The load is a twisted pair
cable that meets IEEE 802.3, Section 14.4.
The TX± signal is filtered on the chip to reduce har-
monic content per Section 14.3.2.1 (10BASE-T). Since
filtering is performed in silicon, TX± can be connected
directly to a standard transformer. External filtering
modules are not needed.
Twisted Pair Receive Function
RX+ ports are differential twisted-pair receivers. When
properly terminated, each RX+ port meets the electrical
18
— Transmit Function
— Receive Function
— Interface Status
— Jabber Function
— Reverse Polarity Detect
Clock
Manchester
Encoder
TX Driver
TX±
Data
(Register 0)
Loopback
Clock
Manchester
RX Driver
Decoder
Squelch
Circuit
RX±
Data
22236G-7
Am79C875
requirements for 10BASE-T receivers as specified in
IEEE 802.3, Section 14.3.1.3. Each receiver has
internal filtering and does not require external filter
modules or common mode chokes.
Signals appearing at the RX± differential input pair are
routed to the internal decoder. The receiver function
meets the propagation delays and jitter requirements
specified by the 10BASE-T Standard. The receiver
squelch level drops to half its threshold value after un-
squelch to allow reception of minimum amplitude sig-
nals and to mitigate carrier fade in the event of worst
case signal attenuation and crosstalk noise conditions.
Twisted Pair Interface Status
The NetPHY™ 4LP transceiver will power up in the
Link Fail state. The Auto-Negotiation algorithm will
apply to allow it to enter the Link Pass state. In the Link
Pass state, receive activity which passes the pulse
width/amplitude requirements of the RX± inputs cause
the PCS Control block to assert Carrier Sense (CRS)
signal at the MII interface.
Jabber Function
The Jabber function inhibits the 10BASE-T twisted pair
transmit function of the NetPHY™ 4LP transceiver de-
vice if the TX± circuits are active for an excessive pe-
riod (20-150 ms). This prevents one port from
disrupting the network due to a stuck-on or faulty trans-
mitter condition. If the maximum transmit time is ex-
ceeded, the data path through the 10BASE-T
transmitter circuitry is disabled (although Link Test
pulses will continue to be sent). The PCS Control block
also sets the Jabber Detect bit in Register 1. Once the
internal transmit data stream from the MENDEC stops,
an unjab time of 250-750 ms will elapse before this
block causes the PCS Control block to re-enable the
transmit circuitry.
When jabber is detected, this block allows the PCS
Control block to assert or de-assert the CRS pin to in-
dicate the current state of the RX± pair. If there is RX±
activity, this block causes the PCS Control block to as-
sert CRS at the RMII. The Jabber function can be dis-
abled by setting Register 24, bit 12.
Reverse Polarity Detect and Correction
Proper 10BASE-T receiver operation requires that the
differential input signal be the correct polarity. That is,
the RX+ line is connected to the RX+ input pin, and the
RX- line is connected to the RX- input pin. Improper
setup of the external wiring can cause the polarity to be
reversed. The NetPHY™ 4LP receivers have the ability
to detect the polarity of the incoming signal and com-
pensate for it. Thus, the proper signal will appear on the
MDI regardless of the polarity of the input signals.
The internal polarity detection and correction circuitry is
set during the reception of the normal link pulses (NLP)
or packets. The receiver detects the polarity of the input