AM79C875KI AMD (ADVANCED MICRO DEVICES), AM79C875KI Datasheet - Page 33

• Manufacturer Part Number: AM79C875KI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C875KI

• Lead Free Status / RoHS Status: Not Compliant

Receive Error Counter (Register 21)
Mode Control Register (Register 24)
Reg
Reg
21
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
15:0
Bit
Bit
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
0
RX_ER Counter
SDCM_SEL
Force 10BASE-T
Link Up
Force
100BASE-TX
Link Up
Jabber Disable
Reserved
Activity LED
Configuration
Reserved
FEFI_Disable
Force FEFI
Transmit
RX_ER_CNT Full
Disable
RX_ER counter
DIS_WDT
EN_RPBK
EN_SCRM
Reserved
FX_SEL
Name
Name
Table 22. Mode Control Register (Register 24)
Table 21. Receive Error Counter (Register 21)
Description
Count of Receive Error Events.
Description
Select Common Mode Voltage Setting for FX Signal Detect (SDI)
input signal.
1 = Select Internal Common Mode Setting.
0 = Select External Common Voltage Setting.
1 = Force link up at 10 Mbps without checking NLP. Auto-
Negotiation must be disabled and the data rate must be 10 Mbps.
0 = Normal Operation.
1 = Force link up at 100 Mbps. Auto-Negotiation must be disabled
and the data rate must be 100 Mbps.
0 = Normal Operation.
1 = Disable Jabber function in PHY.
0 = Enable Jabber function in PHY.
Write as 0, ignore when read.
1 = Activity only responds to receive operation.
0 = Activity responds to Receive and transmit.
In repeater mode, this bit will be ignored.
Write as 0, ignore when read.
Set this bit will disable FEFI generation and detection function. The
default value of this bit is 0 when the chip is working in FX mode.
Otherwise the default value is 1.
This bit is set to force the transmit FEFI pattern.
This bit is set to one to indicate the Receive Error Counter is full.
1 = disable Receive Error Counter.
1 = Disable the watchdog timer in the decipher.
1 = Enable remote loopback, 0 = Disable remote loopback.
0 = Disable data scrambling.
1 = Enable data scrambling.
When FX_DIS pin is asserted low or FX_SEL bit (Register 24.0) is
set to logic high, this bit will be overwritten as “1” automatically.
The default of this bit is set by power on read value of FX_DIS.
Write as 0, ignore when read.
Set this bit to logic 1 to select 100BASE-FX mode, set to logic 0 to
select 100BASE-TX.
Am79C875
RO/RC
Read/
Write
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RW
ANEGA pins
FX_DIS and
SCRAM_EN
0000 (hex)
Default
Default
FX_DIS
Set by
Set by
Set by
pin
pin
0
0
0
0
0
1
0
0
0
0
0
0
0
33