AM79C875KI AMD (ADVANCED MICRO DEVICES), AM79C875KI Datasheet - Page 14

• Manufacturer Part Number: AM79C875KI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C875KI

• Lead Free Status / RoHS Status: Not Compliant

Note: CRS_DV may toggle at 25 MHz starting on a nibble boundary if bits accumulate due to the difference be-
tween CRS and RX_DV. The example waveform shows a single nibble accumulated in the FIFO.
RXD[1:0]
Receive Data [1:0]
RXD[1:0] transitions synchronously to REF_CLK.
Upon assertion of CRS_DV, the PHY will ensure that
RXD[1:0] = 00 until proper receive decoding takes
place. Then for each clock period in which CRS_DV is
asserted, RXD[1:0] transfers two bits of recovered data
from the PHY.
RXD[1:0] in 100 Mbps Mode
For normal reception following assertion of CRS_DV,
RXD[1:0] is “00” until the receiver has determined that
the receive event has a proper Start of Stream Delim-
iter (SSD), which is a /J/K/ pair. Thereafter, preamble
will appear (RXD[1:0] = 01). Data capture by MACs
occur following detection of SFD.
14
REF_CLK
CRS_DV
RXD[1]
RXD[0]
REF_CLK
CRS_DV
RXD[1]
RXD[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
False Carrier detected
/J/
0
0
0
0
Figure 2. 100 Mbps Reception with False Carrier
Figure 1. 100 Mbps Reception with No Errors
1
0
0
0
/K/
1
0
0
0
1
0
0
1
Preamble
1
0
0
1
Am79C875
1
0
0
1
1
0
0
1
If False Carrier is detected (an event starting with any-
thing other than /J/K/), then RXD[1:0] is”10” until the
end of the receive event. This is a unique pattern since
False Carrier can only occur at the beginning of a
packet where a preamble will be decoded (i.e.,
RXD[1:0]=01).
RXD[1:0] in 10 Mbps Mode
Following assertion of CRS_DV, RXD[1:0] shall be “00”
until the 10BASE-T PHY has recovered clock and is
able to decode the receive data. Once valid receive
data is available from the 10BASE-T PHY, RXD[1:0]
takes on the recovered data values (i.e., starting with
“01” for preamble).
At a REF_CLK frequency of 50 MHz, the value on
RXD[1:0] is valid such that RXD[1:0] may be sampled
every tenth cycle, regardless of the starting cycle within
the group and yield the correct frame data.
1
0
0
1
SFD
1
0
0
1
1
0
1
1
1
0
A
A
1
0
B
B
1
0
C
C
Data
1
0
D
D
1
0
E
E
1
0
F
F
0
0
0
0
22236G-4
22236G-3