SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 26
SLXT973QC.A2
Manufacturer Part Number
SLXT973QC.A2
Description
Manufacturer
Intel
Datasheet
1.SLXT973QC.A2.pdf
(88 pages)
Specifications of SLXT973QC.A2
Lead Free Status / RoHS Status
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LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
3.3.8
3.3.8.1
26
Figure 4. Loopback Paths
Table 8.
Carrier Sense, Loopback, and Collision Conditions
Configuration Management Interface
The LXT973 provides an MDIO Management Interface and a Hardware Control Interface for
device configuration and management.
MII Management Interface
The LXT973 supports the IEEE 802.3 MII Management Interface also known as the Management
Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and
control the state of the LXT973. The MDIO interface consists of a physical connection, a specific
protocol which runs across the connection, and an internal set of addressable registers. The
physical interface consists of a data line (MDIO) and clock line (MDC), and a control line
(MDDIS). The maximum speed of MDC is 20 MHz.
100 Mbps
10 Mbps
•
•
1. Test Loopback is enabled when Register bits 0.14 = 1, 0.8 = 1, and 0.12 = 0.
Speed
Register bit 0.8 = 1 (full-duplex)
Register bit 0.12 = 0 (disable auto-negotiation).
Full-Duplex
Full-Duplex
Half-Duplex
Full-Duplex
Full-Duplex
Half-Duplex,
Register bit 16.8 = 0
Half-Duplex,
Register bit 16.8 = 1
MII
Duplex Condition
LXT973
Loopback
10T
Digital
Block
Receive Only
Receive Only
Transmit or Receive
Receive Only
Receive Only
Transmit or Receive
Transmit or Receive
Carrier Sense
Loopback
100X
Analog
Block
Loopback
Test
Yes
Yes
Yes
No
No
No
No
1
Operational
Driver
Driver
Loopback
FX
TX
Yes
No
No
No
No
No
No
Rev. Date: March 1, 2002
Document #: 249426
Transmit and
Transmit and
Transmit and
Collision
Receive
Receive
Receive
Revision #: 002
None
None
None
None
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