SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 28
Manufacturer Part Number
Specifications of SLXT973QC.A2
Lead Free Status / RoHS Status
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Figure 7. Port Address Scheme
Hardware Control Interface
The LXT973 provides a Hardware Control Interface for applications where the MDIO is not
desired. Refer to
The LXT973 requires five power supply inputs: VCCD, VCCR, VCCT, VCCPECL, and VCCIO.
The digital and analog circuits require 2.5V supplies (VCCD, VCCR, and VCCT). These inputs
may be supplied from a single source although decoupling is required to each respective ground.
The fiber VCCPECL supply can be connected to either 2.5V or 3.3V.
A separate power supply may be used for MII and MDIO (VCCIO) interfaces. The power supply
may be either +2.5V or +3.3V. VCCIO should be supplied from the same power source used to
supply the controller on the other side of the interface. As a matter of good practice, these supplies
should be as clean as possible.
Reference Clock / External Oscillator
The LXT973 requires a constant enabled reference clock (REFCLK). REFCLK’s frequency must
be 25 MHz. Considering overall system performance first, the clock is best derived by providing a
crystal-based oscillator. PLL-based oscillators with known stability may also be used. In general,
an oscillator-based clock source is recommended over a derived clock due to frequency stability
Figure 16, “LXT973 Initialization Sequence” on page 47
Example ADDR<4.1> = 0001
PHY ADDR<4.1> (BASE+0)
PHY ADDR<4.1> (BASE+1)
Port 0 = 2
Port 1 = 3
for additional details.
Rev. Date: March 1, 2002
Document #: 249426
Revision #: 002