SLXT973QC.A2 Intel, SLXT973QC.A2 Datasheet - Page 57
Manufacturer Part Number
Specifications of SLXT973QC.A2
Lead Free Status / RoHS Status
Document #: 249426
Revision #: 002
Rev. Date: March 1, 2002
10 Mbps Operation
The LXT973 operates as a standard 10 Mbps transceiver. Data transmitted by the MAC as a 4-bit
nibble is serialized, Manchester-encoded, and transmitted on the twisted-pair outputs
(DPAP/N_0 and DPBP/N_1). Received data is decoded, de-serialized into 4-bit nibbles, and passed
on RXD[3:0] to the MAC across the MII. The LXT973 supports all the standard 10 Mbps
In 10 Mbps mode, the LXT973 always transmits link pulses. If the Link Test Function is enabled, it
monitors the connection for link pulses. Once it detects two to seven link pulses, data transmission
is enabled and remains enabled as long as the link pulses or data reception continues. If the link
pulses stop, the data transmission is disabled.
If the Link Test function is disabled, the LXT973 may transmit packets regardless of detected link
pulses. The Link Test function can be disabled by setting Port Configuration Register bit 16.14.
10Base-T Link Failure Criteria and Override
Link failure occurs if Link Test is enabled and link pulses stop being received. If this condition
occurs, the LXT973 returns to the auto-negotiation phase if auto-negotiation is enabled. If the Link
Integrity Test function is disabled by setting the Port Configuration Register bit 16.14, the LXT973
transmits packets, regardless of link status.
By default, the SQE (heartbeat) function is disabled on the LXT973. To enable this function, set
Register bit 16.9 = 1. When this function is enabled, the LXT973 asserts its COL output for
5 - 15 bit times after each packet. See
If the MAC begins a transmission that exceeds the jabber timer, the LXT973 disables the transmit
and loopback functions and enables the COL pin. The LXT973 automatically exits jabber mode
after 250 - 750 ms. This function can be disabled by setting Register bit 16.10 = 1. See
on page 83
The LXT973 automatically detects and corrects for the condition where the receive signal
(DPBP/N_0 and DPAP/N_1) is inverted. Reversed polarity is detected if 8 inverted link pulses, or 4
inverted end-of-frame markers, are received consecutively. If link pulses or data are not received
for 96-130 ms, the polarity state is reset to a non-inverted state.
for jabber timing parameters.
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
Figure 33 on page 83
for SQE timing parameters.