PIC16F1937-E/MV Microchip Technology, PIC16F1937-E/MV Datasheet - Page 268

• Manufacturer Part Number: PIC16F1937-E/MV
• Description: 14KB Flash, 512B RAM, 256B EEPROM, LCD, 1.8-5.5V 40 UQFN 5x5x0.5mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1937-E/MV

• Processor Series: PIC16F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 14 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-40
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

PIC16(L)F1934/6/7
24.5.6
Clock stretching occurs when a device on the bus
holds the SCL line low, effectively pausing communi-
cation. The slave may stretch the clock to allow more
time to handle data or prepare a response for the mas-
ter device. A master device is not concerned with
stretching as anytime it is active on the bus and not
transferring data it is stretching. Any stretching done
by a slave is invisible to the master software and han-
dled by the hardware that generates SCL.
The CKP bit of the SSPCON1 register is used to con-
trol stretching in software. Any time the CKP bit is
cleared, the module will wait for the SCL line to go low
and then hold it. Setting CKP will release SCL and
allow more communication.
24.5.6.1
Following an ACK if the R/W bit of SSPSTAT is set, a
read request, the slave hardware will clear CKP. This
allows the slave time to update SSPBUF with data to
transfer to the master. If the SEN bit of SSPCON2 is
set, the slave hardware will always stretch the clock
after the ACK sequence. Once the slave is ready, CKP
is set by software and communication resumes.
FIGURE 24-23:
DS41364E-page 268
SSPCON1
WR
SDA
SCL
CKP
Note 1: The BF bit has no effect on whether the
2: Previous versions of the module did not
CLOCK STRETCHING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
clock will be stretched or not. This is differ-
ent than previous versions of the module
that would not stretch the clock, clear
CKP, if SSPBUF was read before the 9th
falling edge of SCL.
stretch the clock for a transmission if
SSPBUF was loaded before the 9th falling
edge of SCL. It is now always cleared for
read requests.
Normal Clock Stretching
CLOCK SYNCHRONIZATION TIMING
DX
Master device
asserts clock
24.5.6.2
In 10-bit Addressing mode, when the UA bit is set, the
clock is always stretched. This is the only time the SCL
is stretched without CKP being cleared. SCL is
released immediately after a write to SSPADD.
24.5.6.3
When the AHEN bit of SSPCON3 is set; CKP is
cleared by hardware after the 8th falling edge of SCL
for a received matching address byte. When the
DHEN bit of SSPCON3 is set; CKP is cleared after the
8th falling edge of SCL for received data.
Stretching after the 8th falling edge of SCL allows the
slave to look at the received address or data and
decide if it wants to ACK the received data.
24.5.7
Any time the CKP bit is cleared, the module will wait
for the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
until the SCL output is already sampled low. There-
fore, the CKP bit will not assert the SCL line until an
external I
SCL line. The SCL output will remain low until the CKP
bit is set and all other devices on the I
released SCL. This ensures that a write to the CKP bit
will not violate the minimum high time requirement for
SCL (see
Master device
releases clock
Note: Previous versions of the module did not
2
stretch the clock if the second address byte
did not match.
Figure
C master device has already asserted the
CLOCK SYNCHRONIZATION AND
THE CKP BIT
10-bit Addressing Mode
Byte NACKing
24-22).
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DX ‚
2
–
C bus have
1