PIC16F1937-E/MV Microchip Technology, PIC16F1937-E/MV Datasheet - Page 40

• Manufacturer Part Number: PIC16F1937-E/MV
• Description: 14KB Flash, 512B RAM, 256B EEPROM, LCD, 1.8-5.5V 40 UQFN 5x5x0.5mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1937-E/MV

• Processor Series: PIC16F
• Core: PIC
• Program Memory Type: Flash
• Program Memory Size: 14 KB
• Data Ram Size: 256 B
• Interface Type: MI2C, SPI, EUSART
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-40
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

PIC16(L)F1934/6/7
TABLE 3-12:
DS41364E-page 40
080h
081h
082h
083h
084h
085h
086h
087h
088h
089h
08Ah
08Bh
08Ch
08Dh
08Eh
08Fh
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
09Fh
Legend:
Note
Address
Bank 1
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
(1, 2)
(2)
1:
2:
3:
4:
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
TRISA
TRISB
TRISC
TRISD
TRISE
PIE1
PIE2
PIE3
—
OPTION_R
EG
PCON
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
—
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
These registers can be addressed from any bank.
These registers/bits are not implemented on PIC16(L)F1936 devices, read as ‘0’.
Unimplemented, read as ‘1’.
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
Working Register
PORTA Data Direction Register
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
Unimplemented
A/D Result Register Low
A/D Result Register High
Unimplemented
TMR1GIE
STKOVF
T1OSCR
SPLLEN
WPUEN
OSFIE
ADFM
Bit 7
GIE
—
—
—
—
—
—
—
—
Write Buffer for the upper 7 bits of the Program Counter
STKUNF
INTEDG
CCP5IE
PLLR
PEIE
ADIE
C2IE
Bit 6
—
—
—
—
—
ADCS<2:0>
TMROCS
TMR0IE
CCP4IE
OSTS
RCIE
Bit 5
C1IE
—
—
—
—
IRCF<3:0>
CHS<4:0>
TMROSE
CCP3IE
HFIOFR
INTE
TXIE
EEIE
Bit 4
TO
—
—
WDTPS<4:0>
TMR6IE
RMCLR
HFIOFL
SSPIE
BCLIE
IOCIE
Bit 3
—
PSA
PD
—
TUN<5:0>
(4)
BSR<4:0>
TRISE2
ADNREF
MFIOFR
TMR0IF
CCP1IE
LCDIE
Bit 2
—
RI
—
Z
(3)
 2008-2011 Microchip Technology Inc.
TRISE1
PS<2:0>
GO/DONE
ADPREF1 ADPREF0 0000 -000 0000 -000
TMR2IE
TMR4IE
LFIOFR
INTF
Bit 1
POR
DC
—
SCS<1:0>
(3)
TRISE0
SWDTEN --01 0110 --01 0110
TMR1IE
HFIOFS
CCP2IE
ADON
IOCIF
Bit 0
BOR
—
C
(3)
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
---- 1111 ---- 1111
0000 0000 0000 0000
0000 00-0 0000 00-0
-000 0-0- -000 0-0-
1111 1111 1111 1111
00-- 11qq qq-- qquu
--00 0000 --00 0000
0011 1-00 0011 1-00
00q0 0q0- qqqq qq0-
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
-000 0000 -000 0000
POR, BOR
Value on
—
—
Value on all
Resets
other
—
—