PIC16LF1828-E/ML Microchip Technology, PIC16LF1828-E/ML Datasheet
PIC16LF1828-E/ML
Specifications of PIC16LF1828-E/ML
Related parts for PIC16LF1828-E/ML
PIC16LF1828-E/ML Summary of contents
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... High-Performance Microcontrollers 2010 Microchip Technology Inc. PIC16(L)F1824/1828 28/40/44-Pin, Low-Power, with nanoWatt XLP Technology Preliminary Data Sheet DS41419B ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Enhanced Low-Voltage Programming (LVP) • Operating Voltage Range: - 1.8V-5.5V (PIC16F1824/1828) - 1.8V-3.6V (PIC16LF1824/1828) • Programmable Code Protection • Power-Saving Sleep mode 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Extreme Low-Power Management PIC16LF1824/1828 with nanoWatt XLP: • Sleep mode • Watchdog Timer: 500 nA • ...
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... PIC16(L)F1824/1828 Peripheral Highlights (Continued): • SR Latch: - Multiple Set/Reset input options - Emulates 555 Timer applications PIC16F/LF1824/1828 Family Types Program Data Memory Memory PIC16LF1824 4K 256 PIC16F1824 4K 256 PIC16LF1828 4K 256 PIC16F1828 4K 256 One pin is input only. Note 1: DS41419B-page 4 256 4/1 256 4/1 256 18 12 ...
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FIGURE 1: 14-PIN DIAGRAM FOR PIC16F/LF1824 PDIP, SOIC, TSSOP (1) (1) CCP2 /P2A /T1CKI/T1OSI/OSC1/CLKIN/RA5 T1G (1) /P2B (1) /SDO (1) /CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 MCLR/V (1) MDCIN2/DT MDOUT/CK (1) /TX (1) /P1B/SRNQ/C2OUT/RC4 (1) (1) (1) (1) MDMIN/SS /P1C /CCP2 /P2A /C12IN3-/CPS7/AN7/RC3 Note 1: ...
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FIGURE 2: 16-PIN DIAGRAM FOR PIC16F/LF1824 QFN (1) (1) CCP2 /P2A /T1CKI/T1OSI/OSC1/CLKIN/RA5 (1) (1) (1) T1G /P2B /SDO /CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 MCLR/V /T1G PP (1) (1) MDCIN2/DT /RX /CCP1/P1A/RC5 Note 1: Pin function is selectable via the APFCON0 or APFCON1 registers. RA0/AN0/CPS0/C1IN+/V ...
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... RC5 5 4 — — — — — — — — — SS Pin function is selectable via the APFCON0 or APFCON1 registers. Note 1: 2010 Microchip Technology Inc. PIC16(L)F1824/1828 C1IN+ — — — TX (1) (1) CK (1) C12IN0- SRI — — RX (1) DT C1OUT SRQ T0CKI CCP3 — ...
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FIGURE 3: 20-PIN DIAGRAM FOR PIC16F/LF1828 PDIP, SOIC, SSOP CCP2 (1) /P2A (1) /T1CKI/T1OSI/OSC1/CLKIN/RA5 T1G (1) /P2B (1) /CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 MDCIN2/DT MDOUT/CK (1) /TX (1) (1) (1) (1) MDMIN/P2A /CCP2 /P1C /C12IN3-/CPS7/AN7/RC3 SS/CCP4/CPS8/AN8/RC6 Note 1: Pin function is selectable via the ...
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FIGURE 4: PIC16F/LF1828 20-PIN QFN QFN MDCIN2/DT (1) MDOUT/CK /TX MDMIN/P2A (1) /CCP2 (1) /P1C Pin function is selectable via the APFCON0 or APFCON1 registers. Note 1: 15 (1) RA1/AN1/CPS1/C12IN0-/V MCLR/V /T1G /RA3 (1) /RX (1) ...
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... Y — — — MDCIN1 Y — — — MDMIN Y — — — MDOUT Y — — — MDCIN2 Y — — — Y — SS SDO — — Y — — — — — — — — — 2010 Microchip Technology Inc. ...
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... Packaging Information.............................................................................................................................................................. 389 Appendix A: Revision History............................................................................................................................................................. 405 Appendix B: Device Differences ........................................................................................................................................................ 405 Index .................................................................................................................................................................................................. 407 The Microchip Web Site ..................................................................................................................................................................... 415 Customer Change Notification Service .............................................................................................................................................. 415 Customer Support .............................................................................................................................................................................. 415 Reader Response .............................................................................................................................................................................. 416 Product Identification System ............................................................................................................................................................ 417 2010 Microchip Technology Inc. PIC16(L)F1824/1828 ) ................................................................................................................................ 333 ™ Preliminary DS41419B-page 11 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com DS41419B-page 12 to receive the most current information on all of our products. Preliminary 2010 Microchip Technology Inc. ...
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... SR Latch Capture/Compare/PWM Modules ECCP1 ECCP2 CCP3 CCP4 Comparators C1 C2 Master Synchronous Serial Ports MSSP Timers Timer0 Timer1 Timer2 Timer4 Timer6 2010 Microchip Technology Inc. PIC16(L)F1824/1828 of the and 1-3 show ● ● ● ● ● ● ● ● ● ● ● ...
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... See applicable chapters for more information on peripherals. Note 1: See Table 1-1 for peripherals available on specific devices. 2: PIC16F/LF1828 only. 3: DS41419B-page 14 Program Flash Memory CPU (Figure 2-1) Timer1 Timer2 Timer4 Timer6 MSSP CCP4 ECCP2 CCP3 Preliminary EEPROM RAM PORTA (3) PORTB PORTC Comparators EUSART 2010 Microchip Technology Inc. ...
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... Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Note 1: Pin functions can be moved using the APFCONO and APFCON1 registers 2: Default function location. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Input Output Type Type TTL CMOS General purpose I/O ...
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... CMOS PWM output. — CMOS SPI data output. ST — Modulator Carrier Input 1. = Schmitt Trigger input with CMOS levels I (Register 12-1 Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels and Register 12-2). 2010 Microchip Technology Inc. ...
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... Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Note 1: Pin functions can be moved using the APFCONO and APFCON1 registers 2: Default function location. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Input Output Type Type TTL CMOS General purpose I/O ...
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... CMOS Clock Reference output. — CMOS PWM output. ST — Timer1 Gate input. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels (Register 12-1 and Register 12-2). 2010 Microchip Technology Inc. ...
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... Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Note 1: Pin functions can be moved using the APFCONO and APFCON1 registers 2: Default function location. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Input Output Type Type TTL CMOS General purpose I/O ...
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... CMOS SPI data output. Power — Positive supply. Power — Ground reference. = Schmitt Trigger input with CMOS levels I (Register 12-1 Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels and Register 12-2). 2010 Microchip Technology Inc. ...
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... Section 3.5 “Indirect Addressing” 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 29.0 “Instruction Set Summary” details. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Saving”, for more for more Preliminary DS41419B-page 21 ...
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... Power-up Timer Oscillator Start-up Timer ALU ALU ALU Power- Reset Watchdog W reg Timer Brown-out Reset Preliminary RAM Addr 12 Indirect Addr 12 FSR0 Reg FSR reg FSR reg STATUS Reg STATUS reg STATUS reg MUX MUX MUX 2010 Microchip Technology Inc. ...
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... Section 11.0 “Data EEPROM and Flash Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device PIC16(L)F1824/1828 2010 Microchip Technology Inc. PIC16(L)F1824/1828 The following features are associated with access and control of program memory and data memory: memory in • PCL and PCLATH • ...
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... If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 7FFFh Preliminary Example 3-1. RETLW INSTRUCTION ;Add Index ;program counter to ;select data ;Index0 data ;Index1 data DATA_INDEX 2010 Microchip Technology Inc. ...
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... File Select Registers (FSR). See Section 3.5 for more information. Addressing” 2010 Microchip Technology Inc. PIC16(L)F1824/1828 3.2.1 CORE REGISTERS The core registers contain the registers that directly affect the basic operation of the PIC16F/LF1824/1828. These registers are listed below: • ...
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... Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. R-1/q R-1/q R/W-0 Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition (1) Preliminary Section 29.0 Summary”). R/W-0/u R/W-0/u (1) ( bit 0 2010 Microchip Technology Inc. ...
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... General Purpose RAM (80 bytes maximum) 6Fh 70h Common RAM (16 bytes) 7Fh 2010 Microchip Technology Inc. PIC16(L)F1824/1828 3.2.5 DEVICE MEMORY MAPS The memory maps for the device family are as shown in Table 3-2. TABLE 3-2: Device PIC16F/LF1824/1828 Section 3 ...
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TABLE 3-3: PIC16F1824/PIC16F1828 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 000h INDF0 080h INDF0 100h 001h INDF1 081h INDF1 101h 002h PCL 082h PCL 102h 003h STATUS 083h STATUS 103h 004h FSR0L 084h FSR0L 104h 005h FSR0H 085h FSR0H ...
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TABLE 3-4: PIC16F1824/PIC16F1828 MEMORY MAP, BANKS 8-15 BANK 8 BANK 9 INDF0 480h INDF0 500h 400h 401h INDF1 481h INDF1 501h 402h PCL 482h PCL 502h 403h STATUS 483h STATUS 503h 404h FSR0L 484h FSR0L 504h 405h FSR0H 485h FSR0H ...
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TABLE 3-5: PIC16F/LF1824/1828 MEMORY MAP, BANKS 16-23 BANK 16 BANK 17 800h INDF0 880h INDF0 900h 801h INDF1 881h INDF1 901h 802h PCL 882h PCL 902h 803h STATUS 883h STATUS 903h 804h FSR0L 884h FSR0L 904h 805h FSR0H 885h FSR0H ...
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TABLE 3-6: PIC16F/LF1824/1828 MEMORY MAP, BANKS 24-31 BANK 24 BANK 25 C00h INDF0 C80h INDF0 D00h C01h INDF1 C81h INDF1 D01h C02h PCL C82h PCL D02h C03h STATUS C83h STATUS D03h C04h FSR0L C84h FSR0L D04h C05h FSR0H C85h FSR0H ...
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... FEDh STKPTR FEEh TOSL FEFh TOSH = Unimplemented data memory locations, Legend: read as ‘0’. DS41419B-page 32 3.2.6 SPECIAL FUNCTION REGISTERS SUMMARY The Special Function Register Summary for the device family are as follows: Device PIC16(L)F1824/1828 Preliminary 2010 Microchip Technology Inc. Bank(s) Page No ...
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... CPSCON1 — — unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. 1: These registers can be addressed from any bank. Note 2: PIC16F/LF1828 only. 3: PIC16F/LF1824 only. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... LFIOFR HFIOFS 10q0 0q00 qqqq qq0q xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu GO/DONE ADON -000 0000 -000 0000 ADPREF<1:0> 0000 -000 0000 -000 — 2010 Microchip Technology Inc. other Resets — — — — ...
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... Unimplemented x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. 1: These registers can be addressed from any bank. Note 2: PIC16F/LF1828 only. 3: PIC16F/LF1824 only. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 — — BSR<4:0> ...
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... OERR RX9D 0000 000x 0000 000x TRMT TX9D 0000 0010 0000 0010 WUE ABDEN 01-0 0-00 01-0 0-00 2010 Microchip Technology Inc. ...
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... Unimplemented x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. 1: These registers can be addressed from any bank. Note 2: PIC16F/LF1828 only. 3: PIC16F/LF1824 only. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 — — BSR<4:0> ...
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... CCP2M1 CCP2M0 0000 0000 0000 0000 P2DC1 P2DC0 0000 0000 0000 0000 PSS2BD1 PSS2BD0 0000 0000 0000 0000 STR2B STR2A ---0 0001 ---0 0001 C1TSEL1 C1TSEL0 0000 0000 0000 0000 — — 2010 Microchip Technology Inc. ...
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... Unimplemented x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. 1: These registers can be addressed from any bank. Note 2: PIC16F/LF1828 only. 3: PIC16F/LF1824 only. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... CLKRDIV<2:0> 0011 0000 0011 0000 — — — MDBIT 0010 ---0 0010 ---0 MDMS<3:0> x--- xxxx u--- uuuu MDCL<3:0> xxx- xxxx uuu- uuuu MDCH<3:0> xxx- xxxx uuu- uuuu 2010 Microchip Technology Inc. other Resets — — — — — — ...
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... Unimplemented x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. 1: These registers can be addressed from any bank. Note 2: PIC16F/LF1828 only. 3: PIC16F/LF1824 only. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... INTF IOCIF 0000 000x 0000 000u — — 2010 Microchip Technology Inc. ...
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... Top-of-Stack High byte TOSH x = unknown unchanged value depends on condition unimplemented reserved. Legend: Shaded locations are unimplemented, read as ‘0’. 1: These registers can be addressed from any bank. Note 2: PIC16F/LF1828 only. 3: PIC16F/LF1824 only. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will 0 be loaded with the address BRW If using BRA, the entire PC will be loaded with the signed value of the operand of the BRA instruction. 0 BRA Preliminary 2010 Microchip Technology Inc. ...
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... RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL TOSH:TOSL 2010 Microchip Technology Inc. PIC16(L)F1824/1828 3.4.1 ACCESSING THE STACK The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack ...
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... Program Counter and pop the stack. 0x09 0x08 0x07 STKPTR = 0x06 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address Preliminary 2010 Microchip Technology Inc. ...
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... The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory 2010 Microchip Technology Inc. PIC16(L)F1824/1828 0x0F Return Address 0x0E Return Address ...
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... Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: DS41419B-page 48 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF 0x7FFF Preliminary 2010 Microchip Technology Inc. ...
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... FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 0000 0x00 0x7F Bank 0 Bank 1 Bank 2 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Indirect Addressing 0 7 FSRxH Bank Select 0001 0010 1111 Bank 31 Preliminary ...
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... FIGURE 3-11: 7 FSRnH 0 1 Location Select 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Bank 2 0x16F 0xF20 Bank 30 0xF6F Preliminary the FSR/INDF interface. All PROGRAM FLASH MEMORY MAP FSRnL 0x8000 0x0000 Program Flash Memory (low 8 bits) 0x7FFF 0xFFFF 2010 Microchip Technology Inc. ...
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... These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. The DEBUG bit in Configuration Word is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 by device Preliminary DS41419B-page 51 ...
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... R/P-1/1 R/P-1/1 R/P-1/1 WDTE1 WDTE0 FOSC2 U = Unimplemented bit, read as ‘1’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit (1) (2) (3) Pin Function Select bit (1) Preliminary R/P-1/1 R/P-1/1 CPD CP bit 7 R/P-1/1 R/P-1/1 FOSC1 FOSC0 bit 0 2010 Microchip Technology Inc. ...
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... Enabling Brown-out Reset does not automatically enable Power-up Timer. Note 1: The entire data EEPROM will be erased when the code protection is turned off during an erase. 2: The entire program memory will be erased when the code protection is turned off. 3: 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Preliminary DS41419B-page 53 ...
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... R/P-1/1 — BORV STVREN R-1 U-1 U-1 — — Unimplemented bit, read as ‘1’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit (1) (2) Preliminary R/P-1/1 U-1 PLLEN — bit 7 R/P-1/1 R/P-1/1 WRT1 WRT0 bit 0 2010 Microchip Technology Inc. ...
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... See Section 11.5 “User ID, Device ID and Configuration for more information on accessing these Word Access” memory locations. For more information on checksum calculation, see the “PIC16F/LF182X/PIC12F/LF1822 Memory Programming Specification” (DS41390). 2010 Microchip Technology Inc. PIC16(L)F1824/1828 “Write such as Preliminary DS41419B-page 55 ...
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... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 13-5 DEV<8:0>: Device ID bits 100111010 = PIC16F1824 100111110 = PIC16F1828 101000010 = PIC16LF1824 101000110 = PIC16LF1828 bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision. This location cannot be written. Note 1: DS41419B-page 56 (1) R ...
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... XT, HS modes) and switch automatically to the internal oscillator. • Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources 2010 Microchip Technology Inc. PIC16(L)F1824/1828 The oscillator module can be configured in one of eight clock modes. 1. ECL – External Clock Low Power mode (0 MHz to 0 ...
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... WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules Preliminary Sleep CPU and T1OSC Peripherals Clock Control FOSC<2:0> SCS<1:0> Clock Source Option for other modules 2010 Microchip Technology Inc. ...
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... Configuration Word 1: • High-power, 4-32 MHz (FOSC = 111) • Medium power, 0.5-4 MHz (FOSC = 110) • Low-power, 0-0.5 MHz (FOSC = 101) 2010 Microchip Technology Inc. PIC16(L)F1824/1828 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...
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... Preliminary CERAMIC RESONATOR OPERATION ( MODE) ® PIC MCU OSC1/CLKIN To Internal Logic R (3) ( Sleep F OSC2/CLKOUT R S (1) ) may be required for S varies with the Oscillator mode F P Oscillator Start-up Timer (OST) Section 5.4 Mode”). 4X PLL Specifications in Section 30.0 2010 Microchip Technology Inc. ) ...
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... MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) • AN1288, “Design Practices for Low-Power External Oscillators” (DS01288) 2010 Microchip Technology Inc. PIC16(L)F1824/1828 5.2.1.6 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required ...
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... OSCSTAT register indicates when the MFINTOSC is running and can be utilized. Preliminary (Register 5-3). Figure 5-1). One of nine Section 5.2.2.7 “Internal for more information. Internal Oscillator Figure 5-1). One of nine Section 5.2.2.7 “Internal for more information. 2010 Microchip Technology Inc. ...
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... Watchdog Timer (WDT) • Fail-Safe Clock Monitor (FSCM) The Low Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 5.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits 5-3) ...
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... Clock switching time delays are shown in Start-up delay specifications are located in the oscillator tables of Specifications”. Preliminary 2010 Microchip Technology Inc. Figure 5-7). If this is the Table 5-1. Section 30.0 “Electrical ...
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... IRCF <3:0> System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Start-up Time HFINTOSC/ MFINTOSC IRCF <3:0> System Clock 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Start-up Time 2-cycle Sync 0 2-cycle Sync LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync ...
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... The Timer1 Oscillator Ready (T1OSCR) bit of the OSCSTAT register indicates whether the Timer1 oscillator is ready to be used. After the T1OSCR bit is set, the SCS bits can be configured to select the Timer1 oscillator. Start-up or Preliminary Section 21.0 for more 2010 Microchip Technology Inc. ...
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... Any clock source LFINTOSC Any clock source Timer1 Oscillator PLL inactive PLL active PLL inactive. Note 1: 2010 Microchip Technology Inc. PIC16(L)F1824/1828 5.4.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: • IESO (of the Configuration Word Inter- nal/External Switchover bit (Two-Speed Start-up mode enabled). • ...
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... CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word 1, or the internal oscillator Preliminary 2010 Microchip Technology Inc. ...
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... The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register ...
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... Clock Monitor Output (Q) OSCFIF The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in Note: this example have been chosen for clarity. DS41419B-page 70 Oscillator Failure Test Test Preliminary Failure Detected Test 2010 Microchip Technology Inc. ...
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... SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Word 1. Duplicate frequency derived from HFINTOSC. Note 1: 2010 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Section 5 ...
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... HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate DS41419B-page 72 R-0/q R-0/q R-q/q HFIOFR HFIOFL MFIOFR U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Conditional Preliminary R-0/0 R-0/q LFIOFR HFIOFS bit 0 2010 Microchip Technology Inc. ...
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... CONFIG1 7:0 CP MCLRE — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. Legend: 2010 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
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... PIC16(L)F1824/1828 NOTES: DS41419B-page 74 Preliminary 2010 Microchip Technology Inc. ...
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... Upon any device Reset, the reference clock module is disabled. The user’s firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 6.3 Conflicts with the CLKR pin ...
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... DS41419B-page 76 R/W-1/1 R/W-0/0 R/W-0/0 CLKRDC<1:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (3) (1) (2) /4. See Section 6.3 “Conflicts with the CLKR pin” Preliminary R/W-0/0 R/W-0/0 CLKRDIV<2:0> bit 0 for details. 2010 Microchip Technology Inc. ...
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... Bit -/7 Bit -/6 13:8 — — CONFIG1 7:0 CP MCLRE — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources. Legend: 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 Bit 2 CLKRDC0 CLKRDIV2 Bit 13/5 Bit 12/4 Bit 11/3 ...
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... PIC16(L)F1824/1828 NOTES: DS41419B-page 78 Preliminary 2010 Microchip Technology Inc. ...
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... SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Overflow/Underflow Reset Stack Pointer External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset BOR Enable 2010 Microchip Technology Inc. PIC16(L)F1824/1828 PWRT Zero 64 ms LFINTOSC PWRTEN Preliminary Device Reset DS41419B-page 79 ...
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... V for a DD BOR , the device BORDC for more information. Device Device Operation upon Operation upon wake-up from release of POR Sleep (1) Waits for BOR ready Waits for BOR ready Begins immediately Begins immediately Begins immediately level. DD 2010 Microchip Technology Inc. ...
Page 81
... If BOREN <1:0> in Configuration Word BOR Enabled 0 = BOR Disabled bit 6-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive 2010 Microchip Technology Inc. PIC16(L)F1824/1828 T BORRDY BOR Protection Active (1) T PWRT < T ...
Page 82
... Upon bringing MCLR high, the device will begin execution immediately (see is useful for testing purposes or to synchronize more than one device operating in parallel. Section 10.0 Table 7-4 Preliminary Timer configuration. See for more information. Figure 7-4). This 2010 Microchip Technology Inc. ...
Page 83
... FIGURE 7-4: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2010 Microchip Technology Inc. PIC16(L)F1824/1828 T PWRT T MCLR T OST Preliminary DS41419B-page 83 ...
Page 84
... Program Counter 0000h ---1 1000 0000h ---u uuuu 0000h ---1 0uuu 0000h ---0 uuuu ---0 0uuu 0000h ---1 1uuu ( ---1 0uuu 0000h ---u uuuu 0000h ---u uuuu 0000h ---u uuuu Preliminary Condition STATUS PCON Register Register 00-- 110x uu-- 0uuu uu-- 0uuu uu-- uuuu uu-- uuuu 00-- 11u0 uu-- uuuu uu-- u0uu 1u-- uuuu u1-- uuuu 2010 Microchip Technology Inc. ...
Page 85
... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2010 Microchip Technology Inc. PIC16(L)F1824/1828 7-2. U-0 R/W/HC-1/q R/W/HC-1/q — ...
Page 86
... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. Note 1: DS41419B-page 86 Bit 5 Bit 4 Bit 3 Bit 2 — — — — — — RMCLR RI — Preliminary Register Bit 1 Bit 0 on Page — BORRDY 81 POR BOR 105 2010 Microchip Technology Inc. ...
Page 87
... A block diagram of the interrupt logic is shown in Figure 8-1 and Figure 8-2. FIGURE 8-1: INTERRUPT LOGIC TMR0IF TMR0IE From Peripheral Interrupt Logic (Figure 8-2) 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE PEIE GIE Preliminary Interrupt to CPU DS41419B-page 87 ...
Page 88
... PERIPHERAL INTERRUPT LOGIC TMR1GIF TMR1GIE ADIF ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE TMR1IF TMR1IE TMR6IF TMR6IE EEIF EEIE OSFIF OSFIE C1IF C1IE C2IF C2IE BCL1IF BCL1IE PIC16F/LF1828 only. Note 1: DS41419B-page 88 Preliminary 2010 Microchip Technology Inc. To Interrupt Logic (Figure 8-1) ...
Page 89
... All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 8.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins ...
Page 90
... Inst(PC) NOP NOP PC+1/FSR New PC/ 0004h ADDR PC+1 Inst(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP Preliminary 0005h Inst(0004h) 0005h Inst(0004h) 0004h 0005h NOP Inst(0004h) Inst(0005h) 0004h 0005h NOP NOP Inst(0004h) 2010 Microchip Technology Inc. ...
Page 91
... Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. 3: CLKOUT not available in all oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in 5: INTF is enabled to be set any time during the Q4-Q1 cycles. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Q2 Q3 ...
Page 92
... Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved. DS41419B-page 92 Preliminary 2010 Microchip Technology Inc. ...
Page 93
... None of the interrupt-on-change pins have changed state The IOCIF Flag bit is read only and cleared when all the Interrupt-on-Change flags in the IOCxF register Note 1: have been cleared by software. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Interrupt flag bits are set when an interrupt Note: ...
Page 94
... Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 R/W-0/0 TXIE SSP1IE CCP1IE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 TMR2IE TMR1IE bit 0 2010 Microchip Technology Inc. ...
Page 95
... Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 Interrupt 0 = Disables the CCP2 Interrupt PIC16F/LF1828 only. Note 1: 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 ...
Page 96
... Note 1: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 U-0 CCP3IE TMR6IE — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 U-0 TMR4IE — bit 0 2010 Microchip Technology Inc. ...
Page 97
... Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register ...
Page 98
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. R/W-0/0 R/W-0/0 U-0 EEIF BCL1IF — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary U-0 U-0 — CCP2IF bit 0 2010 Microchip Technology Inc. ...
Page 99
... TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Note 1: Interrupt flag bits are set when an inter- rupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register ...
Page 100
... RCIF TXIF SSP1IF CCP1IF C1IF EEIF BCL1IF — CCP4IF CCP3IF TMR6IF — Preliminary Register Bit 1 Bit 0 on Page INTF IOCIF 93 PS1 PS0 187 TMR2IE TMR1IE 94 — CCP2IE 95 TMR4IE — 96 TMR2IF TMR1IF 97 — CCP2IF 98 TMR4IF — 99 2010 Microchip Technology Inc. ...
Page 101
... Converter (DAC) Module” Section 14.0 “Fixed for more information on Voltage Reference (FVR)” these modules. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 9.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1. External Reset input on MCLR pin, if enabled 2 ...
Page 102
... Inst(0004h) Register on Bit 1 Bit 0 Page INTF IOCIF 93 IOCAF1 IOCAF0 142 IOCAN1 IOCAN0 142 IOCAP1 IOCAP0 142 — — 144 — — 143 — — 143 TMR2IE TMR1IE 94 — CCP2IE 95 TMR2IF TMR1IF 97 — CCP2IF WDTPS0 SWDTEN 105 2010 Microchip Technology Inc. ...
Page 103
... Configurable time-out period is from 1ms to 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2010 Microchip Technology Inc. PIC16(L)F1824/1828 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41419B-page 103 ...
Page 104
... Active event. See Section 3.0 “Memory Organization” Active The STATUS register information. Disabled Active Disabled Disabled Preliminary Section 5.0 “Oscillator for more and (Register 3-1) for more WDT Cleared Cleared until the end of OST Unaffected 2010 Microchip Technology Inc. ...
Page 105
... SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-1/1 R/W-0/0 R/W-1/1 WDTPS3 WDTPS2 WDTPS1 U = Unimplemented bit, read as ‘0’ -m/n = Value at POR and BOR/Value at all other Resets ...
Page 106
... PIC16(L)F1824/1828 NOTES: DS41419B-page 106 Preliminary 2010 Microchip Technology Inc. ...
Page 107
... When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 11.1 EEADRL and EEADRH Registers The EEADRH:EEADRL register pair can address maximum of 256 bytes of data EEPROM maximum of 32K words of program memory ...
Page 108
... CPU is able to read and write data to the data EEPROM recommended to code-protect the pro- gram memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM. Preliminary 2010 Microchip Technology Inc. (Register 5-1) ...
Page 109
... FLASH PROGRAM MEMORY READ CYCLE EXECUTION Flash ADDR Flash Data INSTR (PC) INSTR( BSF EECON1,RD executed here executed here RD bit EEDATH EEDATL Register EERHLT 2010 Microchip Technology Inc. PIC16(L)F1824/1828 EEADRH,EEADRL PC+3 INSTR ( EEDATH,EEDATL INSTR ( INSTR( Forced NOP executed here executed here Preliminary INSTR ( ...
Page 110
... NOPs. This prevents the user from executing a two-cycle instruction after the RD bit is set. 2: Flash program memory can be read regardless of the setting of the CP bit. Number of Boundary 32 words, = 00000 Preliminary instruction on the next 2010 Microchip Technology Inc. ...
Page 111
... NOP ; Executed NOP ; Ignored BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2010 Microchip Technology Inc. PIC16(L)F1824/1828 (Figure 11-1) (Figure 11-1) Preliminary DS41419B-page 111 ...
Page 112
... If the number of write latches is smaller Note: than the erase block size, the code sequence provided in be repeated multiple times to fully pro- gram an erased program memory row. Preliminary 2010 Microchip Technology Inc. 11-5. The initial address is Example 11-5 may ...
Page 113
... EEADRL<4:0> = 00000 EEADRL<4:0> = 00001 Buffer Register 2010 Microchip Technology Inc. PIC16(L)F1824/1828 continue to run. The processor does not stall when LWLO = 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. ...
Page 114
... Write AAh ; Set WR bit to begin erase ; Any instructions here are ignored as processor ; halts to begin erase sequence ; Processor will stop here and wait for erase complete. ; after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary 2010 Microchip Technology Inc. ...
Page 115
... EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1,WR NOP NOP BCF EECON1,WREN BSF INTCON,GIE 2010 Microchip Technology Inc. PIC16(L)F1824/1828 ; Disable ints so required sequences will execute properly ; Bank 3 ; Load initial address ; ; ; ; Load initial data address ; ; ; Point to program memory ; Not configuration space ; Enable writes ...
Page 116
... Table When read access is initiated on an address outside the parameters listed in register pair is cleared. Function Read Access User IDs Yes Yes Yes Figure 11-1) Figure 11-1) Preliminary 11-2. Table 11-2, the EEDATH:EEDATL Write Access Yes No No 2010 Microchip Technology Inc. ...
Page 117
... EEPROM WRITE VERIFY BANKSEL EEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Preliminary DS41419B-page 117 ...
Page 118
... Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 EEADR<14:8> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u bit 0 R/W-x/u R/W-x/u bit 0 R/W-0/0 R/W-0/0 bit 0 R/W-0/0 R/W-0/0 bit 0 2010 Microchip Technology Inc. ...
Page 119
... RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software Does not initiate a program Flash or data EEPROM data read 2010 Microchip Technology Inc. PIC16(L)F1824/1828 R/W/HC-0/0 R/W-x/q R/W-0/0 ...
Page 120
... WREN EEADRL<7:0> EEADRH<6:0 EEDATL<7:0> EEDATH<5:0> INTE IOCIE TMR0IF EEIE BCL1IE — EEIF BCL1IF — Preliminary W-0/0 W-0/0 bit 0 Register Bit 1 Bit 0 on Page WR RD 119 120* 118 118 118 118 INTF IOCIF 93 — CCP2IE 95 — CCP2IF 98 2010 Microchip Technology Inc. ...
Page 121
... Write PORTx CK Data Register Data Bus Read PORTx To peripherals ANSELx 2010 Microchip Technology Inc. PIC16(L)F1824/1828 12.1 Alternate Pin Function The Alternate Pin Function Control 0 (APFCON0) and Alternate Pin Function Control 1 (APFCON1) registers are used to steer specific peripheral input and output functions between different pins ...
Page 122
... Unimplemented: Read as ‘0’ PIC16F/LF1824 only. Note 1: DS41419B-page 122 U-0 R/W-0/0 R/W-0/0 (1) T1GSEL TXCKSEL — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary U-0 U-0 — — bit 0 2010 Microchip Technology Inc. ...
Page 123
... P2B function is on RC2 1 = P2B function is on RA4 bit 0 CCP2SEL: Pin Selection 0 = CCP2 function is on RC3 1 = CCP2 function is on RA5 2010 Microchip Technology Inc. PIC16(L)F1824/1828 U-0 R/W-0/0 R/W-0/0 P1DSEL P1CSEL — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 124
... PORTA CLRF PORTA BANKSEL LATA CLRF LATA BANKSEL ANSELA CLRF ANSELA BANKSEL TRISA MOVLW B'00111000' ;Set RA<5:3> as inputs MOVWF TRISA Preliminary (Register 12-6) is used to INITIALIZING PORTA ; ;Init PORTA ;Data Latch ; ; ;digital I/O ; ;and set RA<2:0> as ;outputs 2010 Microchip Technology Inc. ...
Page 125
... RA0 1. ICSPDAT 2. ICDDAT 3. DACOUT (DAC) RA1 1. ICSPCLK 2. ICDCLK 3. RX/DT (EUSART) RA2 1. SRQ 2. C1OUT (Comparator) 3. CCP3 RA3 No output priorities. Input only pin. RA4 1. CLKOUT 2. T1OSO 3. CLKR 4. SDO 5. P2B RA5 1. CCP2/P2A 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Preliminary DS41419B-page 125 ...
Page 126
... Value at POR and BOR/Value at all other Resets (1) R/W-1/1 R-1/1 R/W-1/1 TRISA4 TRISA3 TRISA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/x R/W-x/x RA1 RA0 bit 0 R/W-1/1 R/W-1/1 TRISA1 TRISA0 bit 0 2010 Microchip Technology Inc. ...
Page 127
... Digital I/O. Pin is assigned to port or digital special function Analog input. Pin is assigned as analog input When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-x/u U-0 R/W-x/u LATA4 — ...
Page 128
... Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-1/1 INLVLA4 INLVLA3 INLVLA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-1/1 R/W-1/1 WPUA1 WPUA0 bit 0 R/W-0/0 R/W-0/0 INLVLA1 INLVLA0 bit 0 2010 Microchip Technology Inc. ...
Page 129
... Name Bits Bit -/7 Bit -/6 13:8 — — CONFIG1 7:0 CP MCLRE — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA. Legend: 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 Bit 2 — ANSA4 — ANSA2 SSSEL — T1GSEL TXCKSEL — ...
Page 130
... EXAMPLE 12-2: BANKSEL PORTB CLRF PORTB BANKSEL LATB CLRF LATB BANKSEL ANSELB CLRF ANSELB BANKSEL TRISB MOVLW B’11110000’ ;Set RB<7:4> as inputs MOVWF TRISB Preliminary (Register 12-12) is used to INITIALIZING PORTB ; ;Init PORTB ;Data Latch ; ;Make RB<7:4> digital ; ; 2010 Microchip Technology Inc. ...
Page 131
... Certain digital input functions override other port functions and are included in the priority list. RB4 SDA (MSSP) RB5 RX/DT (EUSART) RB6 SCL/SCK (MSSP) RB7 TX/CK (EUSART) 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Preliminary DS41419B-page 131 ...
Page 132
... Value at POR and BOR/Value at all other Resets R/W-x/u U-0 U-0 LATB4 — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary U-0 U-0 — — bit 0 U-0 U-0 — — bit 0 U-0 U-0 — — bit 0 2010 Microchip Technology Inc. ...
Page 133
... INLVLB<7:4>: PORTB Input Level Select bits For RB<7:4> pins, respectively input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change bit 3-0 Unimplemented: Read as ‘0 2010 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-1/1 U-0 U-0 ANSB4 — ...
Page 134
... RB5 RB4 — — TRISB5 TRISB4 — — WPUB5 WPUB4 — — Preliminary (1) Register Bit 1 Bit 0 on Page — — 133 — — 133 — — 132 — — 132 — — 132 — — 133 2010 Microchip Technology Inc. ...
Page 135
... Each weak pull-up is automatically turned off when the port pin is configured as an output. All pull-ups are disabled on a Power-on Reset by the WPUEN bit of the OPTION register. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 12.4.2 ANSELC REGISTER The ANSELC register configure the Input mode of an I/O pin to analog. ...
Page 136
... SDO (MSSP) (PIC16F/LF1824 only) 2. P1D 3. P2B RC3 1. SS (MSSP) (PIC16F/LF1824 only) 2. CCP2 3. P1C 4. P2A RC4 1. MDOUT 2. SRNQ 3. C2OUT 4. TX/CK 5. P1B RC5 1. RX/DT 2. CCP1/P1A RC6 (PIC16F/LF1828 only (MSSP) 2. CCP4 RC7 (PIC16F/LF1828 only) 1. SDO (MSSP) DS41419B-page 136 Preliminary 2010 Microchip Technology Inc. ...
Page 137
... LATC<7:0>: PORTC Output Latch Value bits Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is Note 1: return of actual I/O pin values. LATC<7:6> available on PIC16F/LF1828 only. Otherwise, they are unimplemented and read as ‘0’. 2: 2010 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-x/u R/W-x/u R/W-x/u RC4 ...
Page 138
... Digital input buffer disabled. (1) . Digital input buffer disabled. R/W-1/1 R/W-1/1 R/W-1/1 WPUC4 WPUC3 WPUC2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-1/1 R/W-1/1 ANSC1 ANSC0 bit 0 (1) R/W-1/1 R/W-1/1 WPUC1 WPUC0 bit 0 2010 Microchip Technology Inc. ...
Page 139
... WPUC WPUC7 WPUC6 x = unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. Legend: PIC16F/LF1828 only. Note 1: 2010 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-0/0 R/W-0/0 R/W-1/1 INLVLC4 INLVLC3 INLVLC2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 140
... PIC16(L)F1824/1828 NOTES: DS41419B-page 140 Preliminary 2010 Microchip Technology Inc. ...
Page 141
... CK R RAx IOCAPx 2010 Microchip Technology Inc. PIC16(L)F1824/1828 13.3 Interrupt Flags The IOCAFx and IOCBFx bits located in the IOCAF and IOCBF registers, respectively, are status flags that correspond to the interrupt-on-change pins of the associated port expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set ...
Page 142
... R/W/HS-0/0 IOCAF4 IOCAF3 IOCAF2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HS - Bit is set in hardware Preliminary R/W-0/0 R/W-0/0 IOCAP1 IOCAP0 bit 0 R/W-0/0 R/W-0/0 IOCAN1 IOCAN0 bit 0 R/W/HS-0/0 R/W/HS-0/0 IOCAF1 IOCAF0 bit 0 2010 Microchip Technology Inc. ...
Page 143
... Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt flag will be set upon detecting an edge Interrupt-on-Change disabled for the associated pin. bit 3-0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-0/0 U-0 U-0 IOCBP4 — ...
Page 144
... INLVLA1 INLVLA0 128 133 — — INTF IOCIF 93 IOCAF1 IOCAF0 142 IOCAN1 IOCAN0 142 IOCAP1 IOCAP0 142 — — 144 — — 143 — — 143 TRISA1 TRISA0 126 — — 132 2010 Microchip Technology Inc. ...
Page 145
... FVRCON register. FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> CDAFVR<1:0> FVREN FVRRDY 2010 Microchip Technology Inc. PIC16(L)F1824/1828 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, and DAC is routed through two independent programmable gain amplifiers. Each ...
Page 146
... Value at POR and BOR/Value at all other Resets q = Value depends on condition (1) (3) (3) (High Range) (Low Range for additional information. Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG CDAFVR1 CDAFVR0 Preliminary R/W-0/0 R/W-0/0 ADFVR1 ADFVR0 bit 0 (2) (2) (2) (2) Register Bit 1 Bit 0 on page ADFVR1 ADFVR0 146 2010 Microchip Technology Inc. ...
Page 147
... The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 FIGURE 15-1: 15.2 Minimum Operating V ...
Page 148
... PIC16(L)F1824/1828 NOTES: DS41419B-page 148 Preliminary 2010 Microchip Technology Inc. ...
Page 149
... DAC FVR Buffer1 CHS<4:0> When ADON = 0, all multiplexer inputs are disconnected. Note 1: PIC16F/LF1828 only. 2: 2010 Microchip Technology Inc. PIC16(L)F1824/1828 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. (ADC) allows ADNREF = 1 ...
Page 150
... ADC adversely affect the ADC result. Section 16.2 Preliminary peri- AD Figure 16-3. conversion, the appropriate Section 30.0 “Electrical for more information. Table 16-1 gives , any changes in the RC clock frequency, which may 2010 Microchip Technology Inc. ...
Page 151
... Sleep mode. FIGURE 16-2: ANALOG-TO-DIGITAL CONVERSION Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit 2010 Microchip Technology Inc. PIC16(L)F1824/1828 ) V . DEVICE OPERATING FREQUENCIES AD S Device Frequency (F Device Frequency (F 20 MHz 16 MHz (2) (2) (2) 100 ns 125 ns (2) (2) (2) 200 ns ...
Page 152
... ADCON1 register controls the output format. Figure 16-3 shows the two output formats. for more ADRESH LSB bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 10-bit A/D Result Preliminary ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0 2010 Microchip Technology Inc. ...
Page 153
... A device Reset forces all registers to their Note: Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 16.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...
Page 154
... MOVF ADRESL,W MOVWF RESULTLO Preliminary A/D CONVERSION ; ;clock ;Vdd and Vss Vref ; ;Set RA0 to input ; ;Set RA0 to analog ; ;Turn ADC On ;Acquisiton delay ;No, test again ; ;Read upper 2 bits ;store in GPR space ; ;Read lower 8 bits ;Store in GPR space 2010 Microchip Technology Inc. ...
Page 155
... ADC is disabled and consumes no operating current See Note 1: Section 17.0 “Digital-to-Analog Converter (DAC) See 2: Section 14.0 “Fixed Voltage Reference (FVR)” PIC16F/LF1828 only. 3: 2010 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (2) Module” ...
Page 156
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets SS (1) - pin REF DD (1) + pin REF + pin as the source of the positive reference, be aware that a REF Section 30.0 “Electrical Specifications” Preliminary R/W-0/0 R/W-0/0 ADPREF<1:0> bit 0 for details. 2010 Microchip Technology Inc. ...
Page 157
... Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 158
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u ADRES<9:8> bit 0 R/W-x/u R/W-x/u bit 0 2010 Microchip Technology Inc. ...
Page 159
... REF 2: The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...
Page 160
... V - REF DS41419B-page 160 V DD Sampling Switch 0. Rss R IC LEAKAGE (1) I 0. Full-Scale Range 0.5 LSB Zero-Scale Full-Scale Transition V REF Transition Preliminary HOLD REF Sampling Switch (k) Analog Input Voltage 1.5 LSB + 2010 Microchip Technology Inc. ...
Page 161
... DACLPS DACCON1 — — unknown unchanged, — = unimplemented read as ‘0’ value depends on condition. Shaded cells are not used for ADC Legend: module. PIC16F/LF1828 only. Note 1: 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 Bit 2 CHS3 CHS2 CHS1 CHS0 ADCS1 ADCS0 — ...
Page 162
... PIC16(L)F1824/1828 NOTES: DS41419B-page 162 Preliminary 2010 Microchip Technology Inc. ...
Page 163
... Section 30.0 Specifications”. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 17.3 DAC Voltage Reference Output The DAC can be output to the DACOUT pin by setting the DACOE bit of the DACCON0 register to ‘1’. Selecting the DAC reference voltage for output on the DACOUT pin automatically overrides the digital output buffer and digital input threshold detector functions of that pin ...
Page 164
... VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE ® PIC MCU DAC R Module Voltage Reference Output Impedance DS41419B-page 164 Digital-to-Analog Converter (DAC SRC Steps SRC + DACOUT – Preliminary DACR<4:0> DAC (To Comparator, CSM and ADC Modules) DACOUT DACOE Buffered DAC Output 2010 Microchip Technology Inc. ...
Page 165
... DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DACR<4:0> range select bits are cleared. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 This is also the method used to output the voltage level from the FVR to an output pin. See 17-2: “ ...
Page 166
... Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 DACR<4:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets 5 -))*(DACR<4:0>/( SRC Preliminary U-0 U-0 — DACNSS bit 0 R/W-0/0 R/W-0/0 bit 0 2010 Microchip Technology Inc. ...
Page 167
... Bit 7 Bit 6 FVRCON FVREN FVRRDY DACCON0 DACEN DACLPS DACCON1 — — — = unimplemented, read as ‘0’. Shaded cells are unused by the DAC module. Legend: 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG CDAFVR1 CDAFVR0 DACOE — DACPSS1 DACPSS0 — ...
Page 168
... PIC16(L)F1824/1828 NOTES: DS41419B-page 168 Preliminary 2010 Microchip Technology Inc. ...
Page 169
... Enabling both the Set and Reset inputs Note: from any one source at the same time may result in indeterminate operation, as the Reset dominance cannot be assured. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 18.2 Latch Output The SRQEN and SRNQEN bits of the SRCON0 regis- ter control the Q and Q latch outputs ...
Page 170
... SRRPE SRCLK SRRCKE (3) SYNCC2OUT SRRC2E (3) SYNCC1OUT SRRC1E and simultaneously Note 1: Pulse generator causes a 1 Q-state pulse width. 2: Name denotes the connection point at the comparator output. 3: DS41419B-page 170 SRLEN SRQEN (1) Latch R Q SRLEN SRNQEN Preliminary 2010 Microchip Technology Inc. SRQ SRNQ ...
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... Pulse set input for 1 Q-clock period effect on set input. bit 0 SRPR: Pulse Reset Input of the SR Latch bit 1 = Pulse reset input for 1 Q-clock period effect on reset input. Set only, always reads back ‘0’. Note 1: 2010 Microchip Technology Inc. PIC16(L)F1824/1828 MHz MHz OSC OSC 39 ...
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... C1 Comparator output has no effect on the reset input of the SR latch DS41419B-page 172 R/W-0/0 R/W-0/0 R/W-0/0 SRSC1E SRRPE SRRCKE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 SRRC2E SRRC1E bit 0 2010 Microchip Technology Inc. ...
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... SRSCKE TRISA — — (1) (1) TRISC TRISC7 TRISC6 — = unimplemented, read as ‘0’. Shaded cells are unused by the SR latch module. Legend: PIC16F/LF1828 only. Note 1: 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 Bit 2 — ANSA4 — ANSA2 INLVLA5 INLVLA4 INLVLA3 ...
Page 174
... PIC16(L)F1824/1828 NOTES: DS41419B-page 174 Preliminary 2010 Microchip Technology Inc. ...
Page 175
... When the analog voltage at V less than the analog voltage the output of the IN comparator is a digital low level. When the analog voltage greater than the analog voltage the output of the comparator is a digital high level. IN 2010 Microchip Technology Inc. PIC16(L)F1824/1828 FIGURE 19- ...
Page 176
... DS41419B-page 176 (1) Interrupt Interrupt C POL CxHYS D (from Timer1) T1CLK Preliminary CxINTP det Set CxIF CxINTN det C OUT X To Data Bus Q MC OUT X To ECCP PWM Logic C SYNC TRIS bit C OUT Timer1 or SR Latch SYNCC OUT X 2010 Microchip Technology Inc. ...
Page 177
... The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 19.2.3 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The ...
Page 178
... Section 14.0 “Fixed Voltage Reference (FVR)” for more information on the Fixed Voltage Reference module. See Section 17.0 “Digital-to-Analog (DAC) Module” signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled. Preliminary Converter for more information on the DAC input 2010 Microchip Technology Inc. ...
Page 179
... ECCP Auto-Shutdown mode. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 19.10 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 19-3 ...
Page 180
... Input Capacitance PIN I = Leakage Current at the pin due to various junctions LEAKAGE R = Interconnect Resistance Source Impedance Analog Voltage Threshold Voltage T Note 1: See Section 30.0 “Electrical DS41419B-page 180 V DD 0. (1) LEAKAGE 0. Vss Specifications”. Preliminary To Comparator 2010 Microchip Technology Inc. ...
Page 181
... CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source Comparator output to Timer1 and I/O pin is asynchronous. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-0/0 U-0 R/W-1/1 ...
Page 182
... Value at POR and BOR/Value at all other Resets SS U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 CxNCH<1:0> bit 0 R-0/0 R-0/0 MC2OUT MC1OUT bit 0 2010 Microchip Technology Inc. ...
Page 183
... C2IF TRISA — — (1) (1) TRISC TRISC7 TRISC6 — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module. Legend: PIC16F/LF1828 only. Note 1: 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 Bit 2 C1OE C1POL --- C1SP C2OE C2POL — ...
Page 184
... PIC16(L)F1824/1828 NOTES: DS41419B-page 184 Preliminary 2010 Microchip Technology Inc. ...
Page 185
... From CPSCLK 1 TMR0CS TMR0SE T0XCS 2010 Microchip Technology Inc. PIC16(L)F1824/1828 20.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION register to ‘ ...
Page 186
... Section 30.0 “Electrical Specifications”. 20.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41419B-page 186 Preliminary 2010 Microchip Technology Inc. ...
Page 187
... Timer0 Module Register TRISA — — Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-1/1 R/W-1/1 TMR0SE PSA U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 188
... PIC16(L)F1824/1828 NOTES: DS41419B-page 188 Preliminary 2010 Microchip Technology Inc. ...
Page 189
... T1CKI Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 • Gate Toggle Mode • Gate Single-pulse Mode • Gate Value Status • Gate Event Interrupt Figure 21 block diagram of the Timer1 module ...
Page 190
... T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. T1OSCEN System Clock (F ) OSC x Instruction Clock (F OSC x Capacitive Sensing Oscillator x External Clocking on T1CKI Pin 0 Osc.Circuit On T1OSI/T1OSO Pins 1 Preliminary internal clock source is selected, the system clock or they can run Clock Source /4) 2010 Microchip Technology Inc. ...
Page 191
... A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 21.6 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 Gate circuitry ...
Page 192
... TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 Gate is not enabled (TMR1GE bit is cleared). Preliminary Example 21-5 for timing Figure 21-6 for timing 2010 Microchip Technology Inc. ...
Page 193
... T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2010 Microchip Technology Inc. PIC16(L)F1824/1828 21.9 ECCP/CCP Capture/Compare Time Base The CCP modules use the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode ...
Page 194
... PIC16(L)F1824/1828 FIGURE 21-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 21-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 DS41419B-page 194 Preliminary 2010 Microchip Technology Inc ...
Page 195
... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary Cleared by software DS41419B-page 195 ...
Page 196
... TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41419B-page 196 Set by hardware on falling edge of T1GVAL Preliminary 2010 Microchip Technology Inc. Cleared by hardware on falling edge of T1GVAL Cleared by software ...
Page 197
... This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X. bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 Gate flip-flop 2010 Microchip Technology Inc. PIC16(L)F1824/1828 R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ ...
Page 198
... Comparator 1 optionally synchronized output (SYNCC1OUT Comparator 2 optionally synchronized output (SYNCC2OUT) DS41419B-page 198 R/W-0/u R/W/HC-0/u R-x/x T1GSPM T1GGO/ T1GVAL DONE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HC = Bit is cleared by hardware Preliminary R/W-0/u R/W-0/u T1GSS<1:0> bit 0 2010 Microchip Technology Inc. ...
Page 199
... T1CON TMR1GE T1GPOL T1GCON — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module. Legend: * Page provides register information. PIC16F/LF1828 only. Note 1: 2010 Microchip Technology Inc. PIC16(L)F1824/1828 Bit 5 Bit 4 Bit 3 Bit 2 — ANSA4 — ANSA2 DC1B1 ...
Page 200
... PIC16(L)F1824/1828 NOTES: DS41419B-page 200 Preliminary 2010 Microchip Technology Inc. ...