PIC16LF1828-E/ML Microchip Technology, PIC16LF1828-E/ML Datasheet - Page 325

• Manufacturer Part Number: PIC16LF1828-E/ML
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core, Nan
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1828-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16(L)F1824/1828
26.5
The EUSART will remain active during Sleep only in the
Synchronous Slave mode. All other modes require the
system clock and therefore cannot generate the
necessary signals to run the Transmit or Receive Shift
registers during Sleep.
Synchronous Slave mode uses an externally generated
clock to run the Transmit and Receive Shift registers.
26.5.1
To receive during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCSTA and TXSTA Control registers must be
• If interrupts are desired, set the RCIE bit of the
• The RCIF interrupt flag must be cleared by read-
Upon entering Sleep mode, the device will be ready to
accept data and clocks on the RX/DT and TX/CK pins,
respectively. When the data word has been completely
clocked in by the external device, the RCIF interrupt
flag bit of the PIR1 register will be set. Thereby, waking
the processor from Sleep.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the Global Inter-
rupt Enable (GIE) bit of the INTCON register is also set,
then the Interrupt Service Routine at address 004h will
be called.
DS41419B-page 324
configured for Synchronous Slave Reception (see
Section 26.4.2.4 “Synchronous Slave
Reception
PIE1 register and the GIE and PEIE bits of the
INTCON register.
ing RCREG to unload any pending characters in
the receive buffer.
EUSART Operation During Sleep
SYNCHRONOUS RECEIVE DURING
SLEEP
Setup:”).
Preliminary
26.5.2
To transmit during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCSTA and TXSTA Control registers must be
• The TXIF interrupt flag must be cleared by writing
• If interrupts are desired, set the TXIE bit of the
• Interrupt enable bits TXIE of the PIE1 register and
Upon entering Sleep mode, the device will be ready to
accept clocks on the TX/CK pin and transmit data on
the RX/DT pin. When the data word in the TSR has
been completely clocked out by the external device, the
pending byte in the TXREG will transfer to the TSR and
the TXIF flag will be set. Thereby, waking the processor
from Sleep. At this point, the TXREG is available to
accept another character for transmission, which will
clear the TXIF flag.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit is also set then the Interrupt
Service Routine at address 0004h will be called.
26.5.3
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
registers, APFCON0 and APFCON1. To determine
which pins can be moved and what their default
locations are upon a Reset, see
“Alternate Pin Function”
configured for Synchronous Slave Transmission
(see
Transmission
the output data to the TXREG, thereby filling the
TSR and transmit buffer.
PIE1 register and the PEIE bit of the INTCON reg-
ister.
PEIE of the INTCON register must set.
Section 26.4.2.2 “Synchronous Slave
SYNCHRONOUS TRANSMIT
DURING SLEEP
ALTERNATE PIN LOCATIONS
Setup:”).
 2010 Microchip Technology Inc.
for more information.
Section 12.1