PIC16LF1828-E/ML Microchip Technology, PIC16LF1828-E/ML Datasheet - Page 202

• Manufacturer Part Number: PIC16LF1828-E/ML
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core, Nan
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1828-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16(L)F1824/1828
22.1
The clock input to the Timer2/4/6 modules is the
system instruction clock (F
TMRx increments from 00h on each clock edge.
A 4-bit counter/prescaler on the clock input allows direct
input, divide-by-4 and divide-by-16 prescale options.
These options are selected by the prescaler control bits,
TxCKPS<1:0> of the TxCON register. The value of
TMRx is compared to that of the Period register, PRx, on
each clock cycle. When the two values match, the
comparator generates a match signal as the timer
output. This signal also resets the value of TMRx to 00h
on
counter/postscaler (see
Interrupt”).
The TMRx and PRx registers are both directly readable
and writable. The TMRx register is cleared on any
device Reset, whereas the PRx register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
• a write to the TMRx register
• a write to the TxCON register
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• MCLR Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESET Instruction
22.2
Timer2/4/6 can also generate an optional device
interrupt. The Timer2/4/6 output signal (TMRx-to-PRx
match)
counter/postscaler. This counter generates the TMRx
match interrupt flag which is latched in TMRxIF of the
PIRx register. The interrupt is enabled by setting the
TMRx Match Interrupt Enable bit, TMRxIE of the PIEx
register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, TxOUTPS<3:0>, of the TxCON register.
DS41419B-page 202
Note:
the
Timer2/4/6 Operation
Timer2/4/6 Interrupt
provides
next
TMRx is not cleared when TxCON is
written.
cycle
the
OSC
and
Section 22.2 “Timer2/4/6
input
/4).
drives
for
the
the
output
4-bit
Preliminary
22.3
The unscaled output of TMRx is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSPx modules operating in SPI mode.
Additional information is provided in
“Master Synchronous Serial Port
22.4
The Timer2/4/6 timers cannot be operated while the
processor is in Sleep mode. The contents of the TMRx
and PRx registers will remain unchanged while the
processor is in Sleep mode.
Timer2/4/6 Output
Timer2/4/6 Operation During Sleep
 2010 Microchip Technology Inc.
Module”.
Section 25.0