PIC16LF1828-E/ML Microchip Technology, PIC16LF1828-E/ML Datasheet - Page 66
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PIC16LF1828-E/ML
Manufacturer Part Number
PIC16LF1828-E/ML
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core, Nan
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16F1824-ISL.pdf
(419 pages)
Specifications of PIC16LF1828-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16(L)F1824/1828
5.3
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bits of the OSCCON
register. The following clock sources can be selected
using the SCS bits:
• Default system oscillator determined by FOSC
• Timer1 32 kHz crystal oscillator
• Internal Oscillator Block (INTOSC)
5.3.1
The System Clock Select (SCS) bits of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.
• When the SCS bits of the OSCCON register = 00,
• When the SCS bits of the OSCCON register = 01,
• When the SCS bits of the OSCCON register = 1x,
When switching between clock sources, a delay is
required to allow the new clock to stabilize. These oscil-
lator delays are shown in
5.3.2
The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCSTAT register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<2:0> bits in the Configuration
Word 1, or from the internal clock source. In particular,
OSTS indicates that the Oscillator Start-up Timer
(OST) has timed out for LP, XT or HS modes. The OST
does not reflect the status of the Timer1 Oscillator.
DS41419B-page 66
bits in Configuration Word 1
the system clock source is determined by value of
the FOSC<2:0> bits in the Configuration Word 1.
the system clock source is the Timer1 oscillator.
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always
cleared.
Note:
Clock Switching
SYSTEM CLOCK SELECT (SCS)
BITS
Any automatic clock switch, which may
occur
Fail-Safe Clock Monitor, does not update
the SCS bits of the OSCCON register. The
user can monitor the OSTS bit of the
OSCSTAT register to determine the
current system clock source.
OSCILLATOR START-UP TIME-OUT
STATUS (OSTS) BIT
from
Table
Two-Speed
5-1.
Start-up
Preliminary
or
5.3.3
The Timer1 Oscillator is a separate crystal oscillator
associated with the Timer1 peripheral. It is optimized
for timekeeping operations with a 32.768 kHz crystal
connected between the T1OSO and T1OSI device
pins.
The Timer1 oscillator is enabled using the T1OSCEN
control bit in the T1CON register. See
“Timer1 Module with Gate Control”
information about the Timer1 peripheral.
5.3.4
The user must ensure that the Timer1 Oscillator is
ready to be used before it is selected as a system clock
source. The Timer1 Oscillator Ready (T1OSCR) bit of
the OSCSTAT register indicates whether the Timer1
oscillator is ready to be used. After the T1OSCR bit is
set, the SCS bits can be configured to select the Timer1
oscillator.
TIMER1 OSCILLATOR
TIMER1 OSCILLATOR READY
(T1OSCR) BIT
2010 Microchip Technology Inc.
Section 21.0
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