PIC16LF1828-E/ML Microchip Technology, PIC16LF1828-E/ML Datasheet - Page 326

• Manufacturer Part Number: PIC16LF1828-E/ML
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core, Nan
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1828-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

27.0
The capacitive sensing module allows for an interaction
with an end user without a mechanical interface. In a
typical application, the capacitive sensing module is
attached to a pad on a Printed Circuit Board (PCB),
which is electrically isolated from the end user. When the
end user places their finger over the PCB pad, a
capacitive load is added, causing a frequency shift in the
capacitive sensing module. The capacitive sensing
module requires software and at least one timer
resource to determine the change in frequency. Key
features of this module include:
• Analog MUX for monitoring multiple inputs
• Capacitive sensing oscillator
• Multiple Power modes
• High power range with variable voltage references
• Multiple timer resources
• Software control
• Operation during Sleep
FIGURE 27-1:
 2010 Microchip Technology Inc.
CPS10
CPS11
CPS8
CPS9
Note 1:
CPS0
CPS1
CPS2
CPS3
CPS4
CPS5
CPS6
CPS7
CAPACITIVE SENSING
MODULE
(1)
(1)
(1)
(1)
2:
Reference CPSCON1 register
If CPSON = 0, disabling capacitive sensing, no channel is selected.
CAPACITIVE SENSING BLOCK DIAGRAM
CPSCH<3:0>
CPSON
Ref-
(2)
0
1
Capacitive
Oscillator
CPSOSC
CPSRM
Sensing
DAC
Ref+
CPSRNG<1:0>
(Register
CPSON
0
1
FVR
Ref.
Int.
27-2) for channels implemented on each device.
T0CKI
Preliminary
T0XCS
CPSOUT
CPSCLK
0
1
PIC16F/LF1824/1828
F
OSC
SYNCC1OUT
SYNCC2OUT
T1GSEL<1:0>
T1CS<1:0>
/4
T1OSC/
F
F
T1CKI
T1G
OSC
OSC
0
1
/4
TMR0CS
Timer0 Module
TMR0
Timer1 Module
Control Logic
Timer1 Gate
EN
TMR1H:TMR1L
Overflow
DS41419B-page 325
TMR0IF
Set