PIC16LF1828-E/ML Microchip Technology, PIC16LF1828-E/ML Datasheet - Page 289
PIC16LF1828-E/ML
Manufacturer Part Number
PIC16LF1828-E/ML
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core, Nan
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16F1824-ISL.pdf
(419 pages)
Specifications of PIC16LF1828-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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25.6.13.3
Bus collision occurs during a Stop condition if:
a)
b)
FIGURE 25-38:
FIGURE 25-39:
2010 Microchip Technology Inc.
After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
SDA
SCL
PEN
BCL1IF
P
SSP1IF
SDA
SCL
PEN
BCL1IF
P
SSP1IF
Bus Collision During a Stop
Condition
BUS COLLISION DURING A STOP CONDITION (CASE 1)
BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA asserted low
Assert SDA
T
BRG
T
BRG
Preliminary
T
BRG
T
BRG
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSP1ADD and
counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master
attempting to drive a data ‘0’
PIC16(L)F1824/1828
SCL goes low before SDA goes high,
set BCL1IF
T
(Figure
BRG
T
BRG
25-37). If the SCL pin is sampled
(Figure
SDA sampled
low after T
set BCL1IF
‘0’
‘0’
DS41419B-page 289
‘0’
‘0’
25-38).
BRG
,
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