PIC16LF1828-E/ML Microchip Technology, PIC16LF1828-E/ML Datasheet - Page 254

• Manufacturer Part Number: PIC16LF1828-E/ML
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core, Nan
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1828-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16(L)F1824/1828
25.2.6 SPI OPERATION IN SLEEP MODE
In SPI Master mode, module clocks may be operating
at a different speed than when in Full Power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSP1 clock is much faster than the system clock.
In Slave mode, when MSSP1 interrupts are enabled,
after the master completes sending data, an MSSP1
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSP1 inter-
rupts should be disabled.
TABLE 25-1:
DS41419B-page 254
ANSELA
ANSELB
ANSELC
APFCON0
INLVLA
INLVLA
INLVLB
INLVLC
INLVLC
INTCON
PIE1
PIR1
SSP1BUF
SSP1CON1
SSP1CON3
SSP1STAT
TRISA
TRISA
TRISB
TRISC
TRISC
Legend:
Note
Name
(3)
(4)
(1)
(3)
(4)
(3)
(4)
(1)
(3)
(4)
1:
2:
3:
4:
(1)
*
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP1 in SPI mode.
Page provides register information.
PIC16F/LF1828 only.
PIC16F/LF1824 only.
Unshaded cells apply to PIC16F/LF1828 only.
Unshaded cells apply to PIC16F/LF1824 only.
Synchronous Serial Port Receive Buffer/Transmit Register
INLVLC7
INLVLC7
RXDTSEL
TRISC7
TRISC7
ANSC7
TMR1GIE
TMR1GIF
INLVLB7
ACKTIM
TRISB7
ANSB7
WCOL
Bit 7
SMP
GIE
—
—
—
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
(1)
(1)
(1)
(1)
(1)
SDOSEL
INLVLC6
INLVLC6
TRISC6
TRISC6
ANSC6
INLVLB6
SSPOV
TRISB6
ANSB6
PEIE
ADIE
ADIF
PCIE
Bit 6
CKE
—
—
—
—
—
(1)
(1)
(1)
(1)
(1)
(2)
SSSEL
INLVLA5
INLVLA5
INLVLB5
INLVLC5
INLVLC5
TMR0IE
TRISC5
TRISC5
SSPEN
TRISA5
TRISA5
TRISB5
ANSB5
RCIE
RCIF
SCIE
Bit 5
D/A
—
—
(2)
INLVLC4
INLVLC4
INLVLA4
INLVLA4
INLVLB4
TRISA4
TRISA4
TRISB4
TRISC4
TRISC4
ANSA4
ANSB4
BOEN
Preliminary
INTE
Bit 4
TXIE
TXIF
CKP
—
—
P
INLVLC3
INLVLC3
T1GSEL
INLVLA3
INLVLA3
SSP1IE
SSP1IF
TRISA3
TRISA3
TRISC3
TRISC3
ANSC3
SDAHT
IOCIE
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the
MSSP1 interrupt flag bit will be set and if enabled, will
wake the device.
Bit 3
—
—
—
—
S
TXCKSEL
INLVLA2
INLVLA2
INLVLC2
INLVLC2
TMR0IF
CCP1IE
CCP1IF
SBCDE
TRISA2
TRISA2
TRISC2
TRISC2
ANSA2
ANSC2
Bit 2
R/W
—
—
—
SSPM<3:0>
INLVLA1
INLVLA1
INLVLC1
INLVLC1
TMR2IE
TMR2IF
TRISC1
TRISC1
ANSC1
TRISA1
TRISA1
ANSA1
AHEN
Bit 1
INTF
 2010 Microchip Technology Inc.
UA
—
—
—
—
INLVLA0
INLVLA0
INLVLC0
INLVLC0
TMR1IE
TMR1IF
TRISA0
TRISA0
TRISC0
TRISC0
ANSA0
ANSC0
DHEN
IOCIF
Bit 0
BF
—
—
—
—
Register on
Page
247*
127
133
133
122
128
128
133
139
139
293
295
292
126
126
132
132
132
93
94
97