PIC16LF1828-E/ML Microchip Technology, PIC16LF1828-E/ML Datasheet - Page 187

• Manufacturer Part Number: PIC16LF1828-E/ML
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 18 I/0, Enhanced Mid Range Core, Nan
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1828-E/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 20-1:
TABLE 20-1:
 2010 Microchip Technology Inc.
CPSCON0
FVRCON
INLVLA
INTCON
OPTION_REG WPUEN
TMR0
TRISA
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
R/W-1/1
WPUEN
Name
*
Page provides register information.
Timer0 Module Register
WPUEN: Weak Pull-up Enable bit
1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUx latch values
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
TMR0CS: Timer0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (F
TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
CPSON
FVREN
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
INTEDG
Bit 7
R/W-1/1
GIE
—
—
OPTION_REG: OPTION REGISTER
Bit Value
FVRRDY
INTEDG TMR0CS TMR0SE
CPSRM
000
001
010
011
100
101
110
111
PEIE
Bit 6
—
—
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
TMR0CS
R/W-1/1
Timer0 Rate
INLVLA5 INLVLA4
TMR0IE
TRISA5
TSEN
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Bit 5
—
TMR0SE
R/W-1/1
TSRNG
TRISA4
Preliminary
INTE
Bit 4
—
OSC
/4)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
CPSRNG1 CPSRNG0 CPSOUT
CDAFVR1 CDAFVR0 ADFVR1 ADFVR0
INLVLA3
R/W-1/1
TRISA3
IOCIE
Bit 3
PSA
PSA
PIC16(L)F1824/1828
INLVLA2
TMR0IF
TRISA2
Bit 2
R/W-1/1
PS<2:0>
INLVLA1 INLVLA0
TRISA1
Bit 1
INTF
PS<2:0>
R/W-1/1
TRISA0
T0XCS
IOCIF
Bit 0
DS41419B-page 187
R/W-1/1
Register
on Page
185*
331
146
128
187
126
93
bit 0