MT49H16M18CBM-25 Micron Technology Inc, MT49H16M18CBM-25 Datasheet - Page 10

• Manufacturer Part Number: MT49H16M18CBM-25
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H16M18CBM-25

• Organization: 16Mx18
• Density: 288Mb
• Address Bus: 23b
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: uBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 779mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Table 2:
PDF: 09005aef80a41b59/Source: 09005aef811ba111
288Mb_RLDRAM_II_SIO_D2.fm - Rev. P 1/11 EN
QKx, QKx#
WE#, REF#
BA0–BA2
TMS, TDI
A20–A21
Symbol
DK, DK#
Q0–Q17
A0–A19
CK, CK#
D0–D17
QVLD
V
TDO
V
V
V
TCK
V
A22
CS#
DM
V
V
ZQ
NF
DDQ
EXT
SSQ
REF
DD
TT
SS
Ball Descriptions
Reference External impedance (25–60Ω): This signal is used to tune the device outputs to the system data
Output
Output
Output
Output
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
–
–
–
Address inputs: A0–A19 define the row and column addresses for READ and WRITE operations.
During a MODE REGISTER SET, the address inputs define the register settings. They are sampled
at the rising edge of CK.
Bank address inputs: Select to which internal bank a command is being applied.
Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on
the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.
Chip select: CS# enables the command decoder when LOW and disables it when HIGH. When
the command decoder is disabled, new commands are ignored, but internal operations continue.
Data input: The D signals form the 18-bit input data bus. During WRITE commands, the data is
sampled at both edges of DK.
Input data clock: DK and DK# are the differential input data clocks. All input data is referenced
to both edges of DK. DK# is ideally 180 degrees out of phase with DK. D0–D17 are referenced to
DK and DK#.
Input data mask: The DM signal is the input mask signal for WRITE data. Input data is masked
when DM is sampled HIGH. DM is sampled on both edges of DK. Tie signal to ground if not used.
IEEE 1149.1 clock input: This ball must be tied to V
IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used.
Command inputs: Sampled at the positive edge of CK, WE# and REF# define (together with
CS#) the command to be executed.
Data output: The Q signals form the 18-bit output data bus. During READ commands, the data
is referenced to both edges of QK.
Output data clocks: QKx and QKx# are opposite polarity, output data clocks. They are free-
running, and during READs are edge-aligned with data output from the RLDRAM. QKx# is ideally
180 degrees out of phase with QKx. QK0 and QK0# are aligned with Q0–Q8 and QK1 and QK1#
are aligned with Q9–Q17.
Data valid: The QVLD pin indicates valid output data. QVLD is edge-aligned with QKx and QKx#.
IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if the JTAG function
is not used.
bus impedance. Q output impedance is set to 0.2 × RQ, where RQ is a resistor from this signal to
ground. Connecting ZQ to GND invokes the minimum impedance mode. Connecting ZQ to V
invokes the maximum impedance mode. Refer to Figure 10 on page 32 to activate this function.
Power supply: Nominally 1.8V. See Table 7 on page 18 for range.
DQ power supply: Nominally, 1.5V or 1.8V. Isolated on the device for improved noise immunity.
See Table 7 on page 18 for range.
Power supply: Nominally, 2.5V. See Table 7 on page 18 for range.
Input reference voltage: Nominally V
Ground.
DQ ground: Isolated on the device for improved noise immunity.
Power supply: Isolated termination supply. Nominally, V
range.
Reserved for future use: These signals are internally connected and can be treated as address
inputs.
Reserved for future use: This signal is not connected and can be connected to ground.
No function: These balls can be connected to ground.
288Mb: x18 2.5V V
10
DDQ
Description
Micron Technology, Inc., reserves the right to change products or specifications without notice.
/2. Provides a reference voltage for the input buffers.
EXT
Ball Assignments and Descriptions
, 1.8V V
SS
if the JTAG function is not used.
DDQ
DD
/2. See Table 7 on page 18 for
, HSTL, SIO, RLDRAM II
©2003Micron Technology, Inc. All rights reserved.
DD