MT49H16M18CBM-25 Micron Technology Inc, MT49H16M18CBM-25 Datasheet - Page 18

• Manufacturer Part Number: MT49H16M18CBM-25
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H16M18CBM-25

• Organization: 16Mx18
• Density: 288Mb
• Address Bus: 23b
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: uBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 779mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Input Slew Rate Derating
PDF: 09005aef815b2df8/Source: 09005aef811ba111
288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN
Note:
Table 10 on page 22 and Table 11 on page 23 define the address, command, and data
setup and hold derating values. These values are added to the default
t
the 2 V/ns the nominal setup and hold specifications are based upon.
To determine the setup and hold time needed for a given slew rate, add the
default specification to the “
specification to the “
derated data setup and hold values can be determined in a like manner using the “
V
The derating values on Table 10 and Table 11 apply to all speed grades.
The setup times on Table 10 and Table 11 represent a rising signal. In this case, the time
from which the rising signal crosses V
must be maintained across all slew rates. The derated setup timing represents the point
at which the rising signal crosses V
is calculated by determining the time needed to maintain the given slew rate and the
delta between V
Table 11 are also valid for falling signals (with respect to V
cross point).
The hold times in Table 10 and Table 11 represent falling signals. In this case, the time
from which the falling signal crosses the CK/CK# cross point to when the signal crosses
V
timing represents the delta between the CK/CK# cross point to when the falling signal
crosses V
maintain the given slew rate and the delta between the CK/CK# cross point and V
The hold values in Table 10 and Table 11 are also valid for rising signals (with respect to
V
AH/
REF
IH(DC)
IL[DC]
The above descriptions also pertain to data setup and hold derating when CK/CK# are
replaced with DK/DK#.
t
to CK/CK# Crossing” and “
CH/
MAX and the CK and CK# cross point).
MIN is static and must be maintained across all slew rates. The derated hold
REF(DC)
t
DH specifications when the slew rate of any of these input signals is less than
IH(AC)
. This derated value is calculated by determining the time needed to
288Mb: x18 2.5V V
t
AH/
MIN and the CK/CK# cross point. The setup values in Table 10 and
t
CH CK/CK# Crossing to V
t
AS/
21
t
t
DH to CK/CK# Crossing to V
CS V
REF(DC)
REF
IH(AC)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Electrical Specifications – AC and DC
to CK/CK# Crossing” and the
to the CK/CK# cross point. This derated value
EXT
MIN to the CK/CK# cross point is static and
, 1.8V V
REF
” derated values on Table 10. The
DD
IL[AC]
, HSTL, SIO, RLDRAM II
REF
©2003Micron Technology, Inc. All rights reserved.
MAX and the CK/CK#
” values on Table 11.
t
AS/
t
AH/
t
CS/
t
AS/
t
CH default
t
DS and
t
CS
IH(DC)
t
DS
.