MT49H16M18CBM-25 Micron Technology Inc, MT49H16M18CBM-25 Datasheet - Page 27

• Manufacturer Part Number: MT49H16M18CBM-25
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H16M18CBM-25

• Organization: 16Mx18
• Density: 288Mb
• Address Bus: 23b
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: uBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 779mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Commands
Table 16:
Table 17:
MODE REGISTER SET (MRS)
PDF: 09005aef815b2df8/Source: 09005aef811ba111
288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN
Command
Operation
DSEL/NOP
MRS
READ
WRITE
AREF
Device DESELECT/no operation
MRS
READ
WRITE
AUTO REFRESH
Description of Commands
Command Table
Notes 1 apply to the entire table
The NOP command is used to perform a no operation to the RLDRAM, which essentially
deselects the chip. Use the NOP command to prevent unwanted commands from being
registered during idle or wait states. Operations already in progress are not affected. Output
values depend on command history.
The mode register is set via the address inputs A0–A17. See Figure 10 on page 32 for further
information. The MRS command can only be issued when all banks are idle and no other
operation is in progress.
The READ command is used to initiate a burst read access to a bank. The value on the BA0–
BA2 inputs selects the bank, and the address provided on inputs A0–An selects the data
location within the bank.
The WRITE command is used to initiate a burst write access to a bank. The value on the BA0–
BA2 inputs selects the bank, and the address provided on inputs A0–An selects the data
location within the bank. Input data appearing on the Ds is written to the memory array
subject to the DM input logic level appearing coincident with the data. If the DM signal is
registered LOW, the corresponding data will be written to memory. If the DM signal is
registered HIGH, the corresponding data inputs will be ignored (that is, this part of the data
word will not be written).
The AREF command is used during normal operation of the RLDRAM to refresh the memory
content of a bank. The command is nonpersistent, so it must be issued each time a refresh is
required. The value on the BA0–BA2 inputs selects the bank. The refresh address is
generated by an internal refresh controller, effectively making each address bit a “Don’t
Care” during the AREF command. See “AUTO REFRESH (AREF)” on page 39 for more details.
Notes:
Notes:
The following table provides descriptions of the valid commands of the RLDRAM. All
input states or sequences not shown are illegal or reserved. All command and address
inputs must meet setup and hold times around the rising edge of CK.
1. When the chip is deselected, internal NOP commands are generated and no commands are
2. 288Mb: n = 19.
1. X = “Don’t Care;” H = logic HIGH; L = logic LOW; A = valid address; BA = valid bank address.
2. Only A0–A17 are used for the MRS command.
3. Address width varies with burst length; see for details.
The mode register set stores the data for controlling the operating modes of the memory.
It programs the RLDRAM configuration, burst length, test mode, and I/O options.
During an MRS command, the address inputs A0–A17 are sampled and stored in the
accepted.
DSEL/NOP
WRITE
Code
READ
AREF
MRS
288Mb: x18 2.5V V
CS#
H
L
L
L
L
Description
30
WE#
H
H
X
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
EXT
REF#
, 1.8V V
X
H
H
L
L
OPCODE
A0–An
DD
X
A
A
X
, HSTL, SIO, RLDRAM II
2
©2003Micron Technology, Inc. All rights reserved.
BA0–BA2
BA
BA
BA
X
X
Commands
Notes
Notes
1
2
2
2
3
3