MT49H16M18CBM-25 Micron Technology Inc, MT49H16M18CBM-25 Datasheet - Page 64

• Manufacturer Part Number: MT49H16M18CBM-25
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H16M18CBM-25

• Organization: 16Mx18
• Density: 288Mb
• Address Bus: 23b
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: uBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 779mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

TAP Instruction Set
Overview
EXTEST
IDCODE
High-Z
CLAMP
SAMPLE/PRELOAD
PDF: 09005aef815b2df8/Source: 09005aef811ba111
288Mb_RLDRAM_II_SIO_Core2.fm - Rev. O 1/11 EN
Many different instructions (2
combinations used are listed in Table 28 on page 71. These six instructions are described
in detail below. The remaining instructions are reserved and should not be used.
The TAP controller used in this RLDRAM is fully compliant to the 1149.1 convention.
Instructions are loaded into the TAP controller during the shift-IR state when the
instruction register is placed between TDI and TDO. During this state, instructions are
shifted through the instruction register through the TDI and TDO balls. To execute the
instruction once it is shifted in, the TAP controller needs to be moved into the update-IR
state.
The EXTEST instruction allows circuitry external to the component package to be tested.
Boundary-scan register cells at output balls are used to apply a test vector, while those at
input balls capture test results. Typically, the first test vector to be applied using the
EXTEST instruction will be shifted into the boundary scan register using the PRELOAD
instruction. Thus, during the update-IR state of EXTEST, the output driver is turned on,
and the PRELOAD data is driven onto the output balls.
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the
instruction register. It also places the instruction register between the TDI and TDO balls
and allows the IDCODE to be shifted out of the device when the TAP controller enters
the shift-DR state. The IDCODE instruction is loaded into the instruction register upon
power-up or whenever the TAP controller is given a test logic reset state.
The High-Z instruction causes the boundary scan register to be connected between the
TDI and TDO. This places all RLDRAM outputs into a High-Z state.
When the CLAMP instruction is loaded into the instruction register, the data driven by
the output balls are determined from the values held in the boundary scan register.
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the
TAP controller is in the capture-DR state, a snapshot of data on the inputs and bidirec-
tional balls is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only operate at a frequency up
to 50 MHz, while the RLDRAM clock operates significantly faster. Because there is a large
difference between the clock frequencies, it is possible that during the capture-DR state,
an input or output will undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the device, but there is no guar-
antee as to the value that will be captured. Repeatable results may not be possible.
To ensure that the boundary scan register will capture the correct value of a signal, the
RLDRAM signal must be stabilized long enough to meet the TAP controller’s capture
setup plus hold time (
288Mb: x18 2.5V V
t
CS plus
67
8
t
) are possible with the 8-bit instruction register. All
CH). The RLDRAM clock input might not be captured
IEEE 1149.1 Serial Boundary Scan (JTAG)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
EXT
, 1.8V V
DD
, HSTL, SIO, RLDRAM II
©2003Micron Technology, Inc. All rights reserved.