LSISAS1064 LSI, LSISAS1064 Datasheet - Page 104

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

4-36
PCI Host Register Description
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
Diagnostic Write Enable
The LSISAS1064 sets this read only bit when the host
writes the correct Write I/O Key to the
register. The LSISAS1064 clears this bit when the host
writes a value other than the Write I/O Key to the
Sequence
Flash Bad Signature
The LSISAS1064 sets this bit if the IOP ARM966E-S™
processor encounters a bad Flash signature when
booting from Flash ROM. The LSISAS1064 also sets the
DisARM bit (bit 1 in this register) to hold the IOP ARM
processor in a reset state. The LSISAS1064 maintains
this state until the PCI host clears both the Flash Bad
Signature and DisARM bits.
Reset History
The LSISAS1064 sets this bit if it experiences a Power
On Reset (POR), PCI Reset, or TestReset/.
Diagnostic Read/Write Enable
Setting this bit enables access to the
Read/Write Data
registers.
TTL Interrupt
Setting this bit configures PCI INTA/ as a TTL output.
Clearing this bit configures PCI INTA/ as an open-drain
output. Use this bit for test purposes only.
Reset Adapter
Setting this write only bit causes a hard reset within the
LSISAS1064. The bit self-clears after eight PCI clock
periods. After deasserting this bit, the IOP ARM
processor executes from its default reset vector.
DisARM
Setting this bit disables the ARM processor.
Diagnostic Memory Enable
Setting this bit enables diagnostic memory accesses
through PCI Memory Space [1]. Clearing this bit disables
diagnostic memory accesses to PCI Memory Space [1]
and returns 0xFFFF on reads.
register.
and
Diagnostic Read/Write Address
Diagnostic
Write Sequence
Write
7
6
5
4
3
2
1
0