LSISAS1064 LSI, LSISAS1064 Datasheet - Page 90

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

4-22
31
0
0
0
0
0
0
0
Register: 0xXX
MSI Message Lower Address
Read/Write
PCI Host Register Description
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
24 23
0
0
0
0
0
Multiple Message Capable
These read only bits indicate the number of messages
that the LSISAS1064 requests from the host. The host
system software reads this field to determine the number
of requested messages. The number of requested
messages must align to a power of two. The LSISAS1064
sets this field to 0b000 to request one message. All other
encodings of this field are reserved.
MSI Enable
System software sets this bit to enable MSI. To enable
MSI, the MSI-X bit in the
must also be cleared (‘0’). Setting this bit enables the
device to use MSI to interrupt the host and request ser-
vice. Setting this bit prohibits the LSISAS1064 from using
the INTA/ or ALT_INTA/ pins to request service from the
host. Setting this bit to mask interrupts on the INTA/ or
ALT_INTA/ pins is a violation of the PCI specification.
MSI Message Address
This register contains message address bits [31:2] for the
MSI memory write transaction. The host system specifies
and Dword aligns the message address. During the
address phase, the LSISAS1064 drives Message
Address[1:0] to 0b00.
Reserved
This field is reserved.
0
MSI Message Address
0
0
16 15
0
0
0
0
0
0
MSI-X Message Control
0
0
8
0
7
0
0
0
0
0
register
0
[31:2]
[3:1]
[1:0]
0
0
0
0