LSISAS1064 LSI, LSISAS1064 Datasheet - Page 81

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

31
0
0
0
0
0
0
0
Register: 0x2E–0x2F
Subsystem ID
Read Only
Register: 0x30–0x33
Expansion ROM Base Address
Read/Write
PCI Configuration Space Register Description
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
24 23
0
15
x
0
x
0
0
x
0
Expansion ROM Base Address
x
Subsystem ID
This 16-bit register uniquely identifies the add-in board or
subsystem where this PCI device resides. This register
provides a mechanism for an add-in card vendor to
distinguish their cards from one another even if the cards
use the same PCI controller (and have the same Vendor
ID and Device ID). The board designer can store a
vendor specific, 16-bit value in the NVData image. By
default, the LSISAS1064 loads this register from the
NVData image at power up.
The Subsystem Device ID Control Power-On Sense pin
(MAD[5]) can control the value of bit [15] of this register.
Allowing the Subsystem Device ID Control pin to remain
internally pulled LOW has no effect on this register. Pull-
ing this pin HIGH sets bit [15] of this register. Pulling the
ID Control pin HIGH takes precedence over all other
settings for bit [15].
Refer to
tion,”
0
0
If the ID Control pin is pulled LOW, this register con-
tains 0x1000.
If the ID Control pin is pulled HIGH, this register con-
tains 0x9000.
x
for additional information.
0
16 15
Section 3.11, “Power-On Sense Pins Descrip-
0
x
0
x
0
Subsystem ID
0
8
x
0
x
7
0
0
x
0
x
8
0
7
0
x
0
x
0
0
x
0
0
x
[15:0]
0
4-13
0
x
0
0