LSISAS1064 LSI, LSISAS1064 Datasheet - Page 107

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

31
x
x
x
x
x
x
x
Register: 0x34
Host Interrupt Mask
Read/Write
The Host Interrupt Mask register masks and/or routes the interrupt
conditions that the
PCI I/O Space and Memory Space Register Description
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
24 23
x
x
x
x
x
Reserved
This field is reserved.
Reply Interrupt
The LSISAS1064 sets this bit when the Reply Post FIFO
is not empty. The LSISAS1064 generates a PCI interrupt
when this bit is set and the corresponding mask bit in the
Host Interrupt Mask
Reserved
This field is reserved.
System Doorbell Interrupt
The LSISAS1064 sets this bit when the IOP writes a
value to the System Doorbell. The host can clear this bit
by writing any value to this register. The LSISAS1064
generates a PCI interrupt when this bit is set and the
corresponding mask bit in the
register is cleared.
Reserved
This field is reserved.
Interrupt Request Routing Mode
This field routes PCI interrupts to the INTA/ or ALT_INTA/
pins according to the bit encodings in
host system enables MSI or MSI-X, the LSISAS1064
does not signal PCI interrupts on the INTA/ or ALT_INTA/
pins.
x
Host Interrupt Mask
x
Host Interrupt Status
x
16 15
x
x
x
x
x
register is cleared.
x
register reports.
x
0
Host Interrupt Mask
8
0
7
x
x
Table
x
x
4.9. If the
1
x
[31:10]
[30:4]
x
[2:1]
[9:8]
4-39
0
1
3
0