LSISAS1064 LSI, LSISAS1064 Datasheet - Page 39

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

2.3.2.11
2.3.2.12
2.3.2.13
Configuration Write Command
Memory Read Multiple Command
Split Completion Command
LSISAS1064 by asserting its IDSEL signal when AD[1:0] equal 0b00.
During the address phase of a configuration cycle, AD[7:2] address one
of the 64 Dword registers in the configuration space of each device.
C_BE[3:0]/ address the individual bytes within each Dword register and
determine the type of access to perform. Bits AD[10:8] address the PCI
function Configuration Space (AD[10:8] = 0b000). The LSISAS1064
treats AD[63:11] as logical don’t cares.
The Configuration Write command writes the configuration space of a
device. The LSISAS1064 never generates this command as a master,
but does respond to it as a slave. A device on the PCI bus selects the
LSISAS1064 by asserting its IDSEL signal when bits AD[1:0] equal 0b00.
During the address phase of a configuration cycle, bits AD[7:2] address
one of the 64 Dword registers in the configuration space of each device.
C_BE[3:0]/ address the individual bytes within each Dword register and
determine the type of access to perform. Bits AD[10:8] decode the PCI
function Configuration Space (AD[10:8] = 0b000). The LSISAS1064
treats AD[63:11] as logical don’t cares.
The Memory Read Multiple command is identical to the Memory Read
command, except it additionally indicates that the master intends to fetch
multiple cache lines before disconnecting. The LSISAS1064 supports
PCI Memory Read Multiple functionality when operating in the PCI mode
and determines when to issue a Memory Read Multiple command
instead of a Memory Read command.
Burst Size Selection – The Read Multiple command reads multiple
cache lines of data during a single bus ownership. The number of cache
lines the LSISAS1064 reads is a multiple of the cache line size, which
Revision 3.0 of the PCI specification provides. The LSISAS1064 selects
the largest multiple of the cache line size based on the amount of data
to transfer.
Split transactions in PCI-X replace the delayed transactions in
conventional PCI. The LSISAS1064 supports up to 16 outstanding split
PCI Functional Description
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