LSISAS1064 LSI, LSISAS1064 Datasheet - Page 105

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

31
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register: 0x0C
Test Base Address
Read/Write
The Test Base Address register specifies the base address for Memory
Space [1] accesses.
Register: 0x10
Diagnostic Read/Write Data
Read/Write
This register reads or writes Dword locations on the LSISAS1064 internal
bus. This register is only accessible through PCI I/O Space and returns
0xFFFFFFFF if read through PCI Memory Space. The host can enable
write access to this register by writing the correct Write I/O Key to the
Write Sequence
bit, of the
correct Write I/O Key to the
access to this register.
PCI I/O Space and Memory Space Register Description
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
24 23
24 23
0
0
0
0
0
0
0
0
Host Diagnostic
0
0
Diagnostic Read/Write Data
Test Base Address
The number of significant bits is determined by the size
of the PCI Memory Space [1] in the NVData image.
Reserved
This field is reserved.
Diagnostic Read/Write Data
Using this register, the LSISAS1064 reads/writes data at
the address that the
register specifies.
0
0
register and setting bit 4, the Diagnostic Write Enable
0
0
Test Base Address
0
0
16 15
16 15
0
0
0
0
register. A write of any value other than the
Write Sequence
0
0
0
0
0
0
Diagnostic Read/Write Address
0
0
0
0
0
0
register disables write
8
0
8
0
7
0
7
0
0
0
0
0
0
0
0
0
0
0
[31:10]
[31:0]
0
0
[9:0]
4-37
0
0
0
0