LSISAS1064 LSI, LSISAS1064 Datasheet - Page 33

no-image

LSISAS1064

Manufacturer Part Number
LSISAS1064
Description
Manufacturer
LSI
Datasheet

Specifications of LSISAS1064

Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LSISAS1064 A1
Manufacturer:
LSI
Quantity:
28
Part Number:
LSISAS1064 A3
Manufacturer:
LSI/PBF
Quantity:
202
Part Number:
LSISAS1064/62042D2
Manufacturer:
LSILogic
Quantity:
120
Part Number:
LSISAS1064A2
Manufacturer:
LSI
Quantity:
20 000
Part Number:
LSISAS1064A3
Manufacturer:
LATTICE
Quantity:
628
Part Number:
LSISAS1064A3
Manufacturer:
LSI
Quantity:
20 000
Part Number:
LSISAS1064E
Manufacturer:
ST
Quantity:
2 241
Part Number:
LSISAS1064E
Manufacturer:
LSI
Quantity:
996
Part Number:
LSISAS1064E
Manufacturer:
LSI
Quantity:
20 000
Company:
Part Number:
LSISAS1064E
Quantity:
2 833
Part Number:
LSISAS1064E B1
Manufacturer:
LSI
Quantity:
110
Part Number:
LSISAS1064E B1
Manufacturer:
LSI/PBF
Quantity:
654
Part Number:
LSISAS1064E B1
Manufacturer:
LSILOGI
Quantity:
20 000
Company:
Part Number:
LSISAS1064E B1
Quantity:
798
Part Number:
LSISAS1064E B3
Manufacturer:
LSI
Quantity:
59
Part Number:
LSISAS1064E B3
Manufacturer:
LSI
Quantity:
147
Part Number:
LSISAS1064E B3
Manufacturer:
LSI
Quantity:
20 000
Part Number:
LSISAS1064E-B3
Quantity:
3
2.1.2.5
2.1.2.6
2.1.3
2.2
Fusion-MPT Architecture Overview
Context RAM
SAS Link and Phy
Quad Port DMA Arbiter
The LSISAS1064 uses the Gflx GigaBlaze transceivers to implement the
SAS link. The SAS link layer manages SAS connections between initiator
and target ports, data clocking, and CRC checking on received data. The
SAS link is also responsible for starting a link reset sequence.
The SAS phys interface to the physical layer, perform serial-to-parallel
conversion of received data and parallel-to-serial conversion of transmit
data, manage phy reset sequences, and perform 8b/10b encoding.
The quad port arbiter interfaces with the host interface DMA arbiter and
determines bus priority between each of the four ports for DMA transfers.
The context RAM is a memory that is shared between the host interface
module and the quad port module. The context RAM contains the
message frames, the FIFOs, and a portion of the firmware.
The Fusion-MPT architecture provides two I/O methods for the host
system to communicate with the IOP: the system interface doorbell and
the message queues.
The system interface doorbell is a simple message passing mechanism
that allows the PCI host system and IOP to exchange single 32-bit
Dword messages. When the host system writes to the doorbell, the
LSISAS1064 hardware generates a maskable interrupt to the IOP, which
can then read the doorbell value and take the appropriate action. When
the IOP writes a value to the doorbell, the LSISAS1064 hardware
generates a maskable interrupt to the host system. The host system can
then read the doorbell value and take the appropriate action.
There are two, 32-bit message queues: the request message queue and
the reply message queue. The host uses the request queue to request
an action by the LSISAS1064, and the LSISAS1064 uses the reply
queue to return status information to the host. The request message
Fusion-MPT Architecture Overview
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
2-7

Related parts for LSISAS1064