LSISAS1064 LSI, LSISAS1064 Datasheet - Page 141

• Manufacturer Part Number: LSISAS1064
• Manufacturer: LSI

Specifications of LSISAS1064

• Lead Free Status / RoHS Status: Not Compliant

DC characteristics
designed maximum cumulative read size bit
designed maximum memory read byte count bit
designed maximum outstanding split transactions
detected parity error (from slave) bit
device complexity bit
device driver stability
device ID configuration 3-14,
device ID register
device number bit
device specific initialization bit
DEVSEL/ 3-5,
DEVSEL/ timing bit
diagnostic memory
diagnostic memory enable bit
diagnostic read/write address register 4-35, 4-36,
diagnostic read/write data register 4-35, 4-36,
diagnostic read/write enable bit
diagnostic write enable bit 4-35, 4-36,
DisARM bit
DMA
doorbell 2-7,
drawing
dual address cycles command 2-8, 2-11,
E
electrostatic discharge
enable
ESD
4-30
bit
4-38
4-37,
host
interrupt mask bit
status bit
system 4-34,
system interface
system interrupt bit
package 5-18,
bus mastering bit
diagnostic memory bit
diagnostic write bit
I/O space bit
memory space bit
MSI bit
parity error response bit
write and invalidate bit
5-2
2-15
4-30
4-34
4-38
4-22
4-36
4-38
2-8
5-3
4-38
4-5
5-19
4-3
4-32
5-1
4-32
4-6
2-7
4-4
4-40
4-31
4-5
1-6
Index
Copyright © 2003–2005 by LSI Logic Corporation. All rights reserved.
4-36
4-39
5-2
4-36
4-4
4-4
3-15
4-36
4-18
4-36
4-5
4-38
2-14
4-30
expansion ROM base address
expansion ROM base address register
expansion ROM enable bit
external
F
FAULT_LED[3:0]/ 3-10,
FIFO
flash ROM
flash ROM size
FLASH_CS/ 3-9,
FRAME/ 3-5,
frames
FSELA 3-10, 3-16,
function number bit
Fusion-MPT 1-1, 1-4, 1-5, 2-1, 2-3, 2-7,
G
general description
GNT/ 2-23, 3-5,
GPIO[3:0] 3-10,
GPIO[7:0]
H
HB_LED/ 3-10,
header type register
high priority request FIFO
high priority request MFA
host diagnostic register 4-35,
host doorbell value
host interface module 2-2,
host interrupt mask register 2-16, 3-6,
host interrupt status register 4-38,
host system
hot swap enable 3-14,
clock
memory interface
memory interface timing diagrams
reply free
reply post 2-8,
request post
bad signature bit
signature recognition
size
reply message 2-8,
request message 2-8,
2-4
3-14
5-8
3-16
2-7
2-8
5-3
5-5
2-8
3-15
5-7
5-3
5-6
4-39
5-5
1-1
4-34
4-32
4-36
4-9
2-19
2-15
3-15
5-5
2-21
2-15
4-41
2-4
2-3
4-14
4-38
4-5
4-39
5-10
4-39
4-13
4-32
IX-3