S9S08SG16E1CTJ Freescale, S9S08SG16E1CTJ Datasheet - Page 136

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S9S08SG16E1CTJ

Manufacturer Part Number
S9S08SG16E1CTJ
Description
Manufacturer
Freescale
Datasheet

Specifications of S9S08SG16E1CTJ

Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
SCI/SPI
Total Internal Ram Size
1KB
# I/os (max)
16
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
20
Package Type
TSSOP
Program Memory Type
Flash
Program Memory Size
16KB
Lead Free Status / RoHS Status
Compliant
Chapter 9 Analog-to-Digital Converter (S08ADC10V1)
9.3.9
The pin control registers disable the digital interface to the associated MCU pins used as analog inputs to
reduce digital noise and improve conversion accuracy. APCTL2 controls channels 8–15 of the ADC
module. This register is not implemented on MCUs that do not have associated external analog inputs.
Consult the ADC channel assignment in the module introduction for information on availability of this
register.
136
ADPC15
ADPC14
ADPC13
ADPC12
ADPC11
ADPC10
ADPC1
ADPC0
Field
Field
7
6
5
4
3
2
1
0
Reset:
W
ADC Pin Control 15 — ADPC15 controls the pin associated with channel AD15.
0 AD15 pin I/O control enabled
1 AD15 pin I/O control disabled
ADC Pin Control 14 — ADPC14 controls the pin associated with channel AD14.
0 AD14 pin I/O control enabled
1 AD14 pin I/O control disabled
ADC Pin Control 13 — ADPC13 controls the pin associated with channel AD13.
0 AD13 pin I/O control enabled
1 AD13 pin I/O control disabled
ADC Pin Control 12 — ADPC12 controls the pin associated with channel AD12.
0 AD12 pin I/O control enabled
1 AD12 pin I/O control disabled
ADC Pin Control 11 — ADPC11 controls the pin associated with channel AD11.
0 AD11 pin I/O control enabled
1 AD11 pin I/O control disabled
ADC Pin Control 10 — ADPC10 controls the pin associated with channel AD10.
0 AD10 pin I/O control enabled
1 AD10 pin I/O control disabled
R
Pin Control 2 Register (APCTL2)
ADC Pin Control 1 — ADPC1 controls the pin associated with channel AD1.
0 AD1 pin I/O control enabled
1 AD1 pin I/O control disabled
ADC Pin Control 0 — ADPC0 controls the pin associated with channel AD0.
0 AD0 pin I/O control enabled
1 AD0 pin I/O control disabled
ADPC15
7
0
Table 9-10. APCTL1 Register Field Descriptions (continued)
ADPC14
0
Table 9-11. APCTL2 Register Field Descriptions
6
Figure 9-11. Pin Control 2 Register (APCTL2)
ADPC13
MC9S08SG32 Data Sheet, Rev. 8
0
5
ADPC12
0
4
Description
Description
ADPC11
0
3
ADPC10
0
2
ADPC9
Freescale Semiconductor
0
1
ADPC8
0
0

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