S9S08SG16E1CTJ Freescale, S9S08SG16E1CTJ Datasheet - Page 254

• Manufacturer Part Number: S9S08SG16E1CTJ
• Manufacturer: Freescale

Specifications of S9S08SG16E1CTJ

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 16
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Lead Free Status / RoHS Status: Compliant

Chapter 16 Timer/PWM Module (S08TPMV3)
16.3.5
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel registers are cleared by
reset.
254
ELSnB
ELSnA
MSnA
Field
3–2
4
Mode select A for TPM channel n. When CPWMS=0 and MSnB=0, MSnA configures TPM channel n for
input-capture mode or output compare mode. Refer to
controls.
Note: If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
Edge/level select bits. Depending upon the operating mode for the timer channel as set by CPWMS:MSnB:MSnA
and shown in
the level that will be driven in response to an output compare match, or select the polarity of the PWM output.
Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general purpose I/O pin not related to any timer
functions. This function is typically used to temporarily disable an input capture channel or to make the timer pin
available as a general purpose I/O pin when the associated timer channel is set up as a software timer that does
not require the use of a pin.
TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)
CPWMS
X
0
1
mode, it is possible to get an unexpected indication of an edge trigger.
Table
MSnB:MSnA
Table 16-6. TPMxCnSC Field Descriptions (continued)
16-7, these bits select the polarity of the input edge that triggers an input capture event, select
XX
XX
1X
00
01
Table 16-7. Mode, Edge, and Level Selection
MC9S08SG32 Data Sheet, Rev. 8
ELSnB:ELSnA
X1
X1
00
01
10
11
00
01
10
11
10
10
Description
Output compare
Center-aligned
Input capture
Edge-aligned
Table 16-7
Pin not used for TPM - revert to general
purpose I/O or other peripheral control
Mode
PWM
PWM
for a summary of channel mode and setup
Capture on falling edge
Software compare only
Capture on rising edge
Set output on compare
High-true pulses (clear
High-true pulses (clear
output on compare-up)
output on compare-up)
Low-true pulses (set
Low-true pulses (set
Capture on rising or
output on compare)
output on compare)
Toggle output on
Clear output on
Configuration
falling edge
compare
compare
only
only
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